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fixup! Add sf. prefix.
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‎llvm/docs/RISCVUsage.rst

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -363,10 +363,10 @@ The current vendor extensions supported are:
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LLVM implements `version 1.0.0 of the CORE-V immediate branching custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/cv32e40p_v1.3.2/docs/source/instruction_set_extensions.rst>`__ by OpenHW Group. All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time.
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``XSiFivecdiscarddlone``
366-
LLVM implements `the SiFive cdiscard.d.l1 instruction specified in <https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf>`_ by SiFive.
366+
LLVM implements `the SiFive sf.cdiscard.d.l1 instruction specified in <https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf>`_ by SiFive.
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``XSiFivecflushdlone``
369-
LLVM implements `the SiFive cflush.d.l1 instruction specified in <https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf>`_ by SiFive.
369+
LLVM implements `the SiFive sf.cflush.d.l1 instruction specified in <https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf>`_ by SiFive.
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Experimental C Intrinsics
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=========================

‎llvm/lib/Target/RISCV/RISCVFeatures.td

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1060,19 +1060,19 @@ def HasVendorXSfvfnrclipxfqf
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def FeatureVendorXSiFivecdiscarddlone
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: SubtargetFeature<"xsifivecdiscarddlone", "HasVendorXSiFivecdiscarddlone", "true",
1063-
"'XSiFivecdiscarddlone' (SiFive cdiscard.d.l1 Instruction)", []>;
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"'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction)", []>;
10641064
def HasVendorXSiFivecdiscarddlone
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: Predicate<"Subtarget->hasVendorXSiFivecdiscarddlone()">,
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AssemblerPredicate<(all_of FeatureVendorXSiFivecdiscarddlone),
1067-
"'XSiFivecdiscarddlone' (SiFive cdiscard.d.l1 Instruction)">;
1067+
"'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction)">;
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10691069
def FeatureVendorXSiFivecflushdlone
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: SubtargetFeature<"xsifivecflushdlone", "HasVendorXSiFivecflushdlone", "true",
1071-
"'XSiFivecflushdlone' (SiFive cflush.d.l1 Instruction)", []>;
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"'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction)", []>;
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def HasVendorXSiFivecflushdlone
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: Predicate<"Subtarget->hasVendorXSiFivecflushdlone()">,
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AssemblerPredicate<(all_of FeatureVendorXSiFivecflushdlone),
1075-
"'XSiFivecflushdlone' (SiFive cflush.d.l1 Instruction)">;
1075+
"'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction)">;
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// Core-V Extensions
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‎llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -814,7 +814,7 @@ let Predicates = [HasVendorXSiFivecdiscarddlone] in {
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DecoderNamespace = "XSiFivecdiscarddlone" in
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def SF_CDISCARD_D_L1
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: RVInstR<0b1111110, 0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1),
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"cdiscard.d.l1", "$rs1">, Sched<[]> {
817+
"sf.cdiscard.d.l1", "$rs1">, Sched<[]> {
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let rd = 0;
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let rs2 = 0b00010;
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}
@@ -825,7 +825,7 @@ let Predicates = [HasVendorXSiFivecflushdlone] in {
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DecoderNamespace = "XSiFivecflushdlone" in
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def SF_CFLUSH_D_L1
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: RVInstR<0b1111110, 0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1),
828-
"cflush.d.l1", "$rs1">, Sched<[]> {
828+
"sf.cflush.d.l1", "$rs1">, Sched<[]> {
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let rd = 0;
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let rs2 = 0b00000;
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}

‎llvm/test/MC/RISCV/xsifive-invalid.s

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,10 @@
11
# RUN: not llvm-mc -triple riscv32 < %s 2>&1 | FileCheck %s
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# RUN: not llvm-mc -triple riscv64 < %s 2>&1 | FileCheck %s
33

4-
cflush.d.l1 x0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSiFivecflushdlone' (SiFive cflush.d.l1 Instruction){{$}}
4+
sf.cflush.d.l1 x0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction){{$}}
55

6-
cflush.d.l1 x7 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSiFivecflushdlone' (SiFive cflush.d.l1 Instruction){{$}}
6+
sf.cflush.d.l1 x7 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction){{$}}
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8-
cdiscard.d.l1 x0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSiFivecdiscarddlone' (SiFive cdiscard.d.l1 Instruction){{$}}
8+
sf.cdiscard.d.l1 x0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction){{$}}
99

10-
cdiscard.d.l1 x7 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSiFivecdiscarddlone' (SiFive cdiscard.d.l1 Instruction){{$}}
10+
sf.cdiscard.d.l1 x7 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction){{$}}

‎llvm/test/MC/RISCV/xsifive-valid.s

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -9,18 +9,18 @@
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# RUN: | llvm-objdump --mattr=+xsifivecdiscarddlone,+xsifivecflushdlone -M no-aliases -d - \
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# RUN: | FileCheck -check-prefix=CHECK-INST %s
1111

12-
# CHECK-INST: cflush.d.l1 zero
12+
# CHECK-INST: sf.cflush.d.l1 zero
1313
# CHECK-ENC: encoding: [0x73,0x00,0x00,0xfc]
14-
cflush.d.l1 x0
14+
sf.cflush.d.l1 x0
1515

16-
# CHECK-INST: cflush.d.l1 t2
16+
# CHECK-INST: sf.cflush.d.l1 t2
1717
# CHECK-ENC: encoding: [0x73,0x80,0x03,0xfc]
18-
cflush.d.l1 x7
18+
sf.cflush.d.l1 x7
1919

20-
# CHECK-INST: cdiscard.d.l1 zero
20+
# CHECK-INST: sf.cdiscard.d.l1 zero
2121
# CHECK-ENC: encoding: [0x73,0x00,0x20,0xfc]
22-
cdiscard.d.l1 x0
22+
sf.cdiscard.d.l1 x0
2323

24-
# CHECK-INST: cdiscard.d.l1 t2
24+
# CHECK-INST: sf.cdiscard.d.l1 t2
2525
# CHECK-ENC: encoding: [0x73,0x80,0x23,0xfc]
26-
cdiscard.d.l1 x7
26+
sf.cdiscard.d.l1 x7

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