Skip to content

Commit f5e2cc4

Browse files
committed
Add extension xandesperf for A25/AX25
1 parent 1013fbe commit f5e2cc4

File tree

3 files changed

+8
-4
lines changed

3 files changed

+8
-4
lines changed

clang/test/Driver/print-enabled-extensions/riscv-andes-a25.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,8 @@
2323
// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation)
2424
// CHECK-NEXT: zbc 1.0 'Zbc' (Carry-Less Multiplication)
2525
// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions)
26+
// CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension)
2627
// CHECK-EMPTY:
2728
// CHECK-NEXT: Experimental extensions
2829
// CHECK-EMPTY:
29-
// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0
30+
// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0_xandesperf5p0

clang/test/Driver/print-enabled-extensions/riscv-andes-ax25.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,8 @@
2222
// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation)
2323
// CHECK-NEXT: zbc 1.0 'Zbc' (Carry-Less Multiplication)
2424
// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions)
25+
// CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension)
2526
// CHECK-EMPTY:
2627
// CHECK-NEXT: Experimental extensions
2728
// CHECK-EMPTY:
28-
// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0
29+
// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0_xandesperf5p0

llvm/lib/Target/RISCV/RISCVProcessors.td

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -660,7 +660,8 @@ def ANDES_A25 : RISCVProcessorModel<"andes-a25",
660660
FeatureStdExtD,
661661
FeatureStdExtC,
662662
FeatureStdExtB,
663-
FeatureStdExtZbc]>;
663+
FeatureStdExtZbc,
664+
FeatureVendorXAndesPerf]>;
664665

665666
def ANDES_AX25 : RISCVProcessorModel<"andes-ax25",
666667
NoSchedModel,
@@ -674,7 +675,8 @@ def ANDES_AX25 : RISCVProcessorModel<"andes-ax25",
674675
FeatureStdExtD,
675676
FeatureStdExtC,
676677
FeatureStdExtB,
677-
FeatureStdExtZbc]>;
678+
FeatureStdExtZbc,
679+
FeatureVendorXAndesPerf]>;
678680

679681
def ANDES_N45 : RISCVProcessorModel<"andes-n45",
680682
NoSchedModel,

0 commit comments

Comments
 (0)