Skip to content

Commit f652754

Browse files
committed
Fixups
1 parent d04e63c commit f652754

File tree

1 file changed

+0
-18
lines changed

1 file changed

+0
-18
lines changed

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 0 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -19107,23 +19107,10 @@ tryToReplaceScalarFPConversionWithSVE(SDNode *N, SelectionDAG &DAG,
1910719107
!isSupportedType(N->getOperand(0).getValueType()))
1910819108
return SDValue();
1910919109

19110-
// Look through fp_extends to avoid extra fcvts.
1911119110
SDValue SrcVal = N->getOperand(0);
19112-
if (SrcVal->getOpcode() == ISD::FP_EXTEND &&
19113-
isSupportedType(SrcVal->getOperand(0).getValueType()))
19114-
SrcVal = SrcVal->getOperand(0);
19115-
1911619111
EVT SrcTy = SrcVal.getValueType();
1911719112
EVT DestTy = N->getValueType(0);
1911819113

19119-
// Merge in any subsequent fp_round to avoid extra fcvts.
19120-
SDNode *FPRoundNode = nullptr;
19121-
if (N->hasOneUse() && N->use_begin()->getOpcode() == ISD::FP_ROUND &&
19122-
isSupportedType(N->use_begin()->getValueType(0))) {
19123-
FPRoundNode = *N->use_begin();
19124-
DestTy = FPRoundNode->getValueType(0);
19125-
}
19126-
1912719114
EVT SrcVecTy;
1912819115
EVT DestVecTy;
1912919116
if (DestTy.bitsGT(SrcTy)) {
@@ -19145,11 +19132,6 @@ tryToReplaceScalarFPConversionWithSVE(SDNode *N, SelectionDAG &DAG,
1914519132
SDValue Convert = DAG.getNode(N->getOpcode(), DL, DestVecTy, Vec);
1914619133
SDValue Scalar =
1914719134
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, DestTy, Convert, ZeroIdx);
19148-
19149-
if (FPRoundNode) {
19150-
DAG.ReplaceAllUsesWith(SDValue(FPRoundNode, 0), Scalar);
19151-
return SDValue();
19152-
}
1915319135
return Scalar;
1915419136
}
1915519137

0 commit comments

Comments
 (0)