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[MLIR][AMDGPU] Remove support for old llvm.amdgcn.buffer.* intrinsics (#93838)
They have been superseded by llvm.amdgcn.raw.buffer.* and llvm.amdgcn.struct.buffer.*.
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‎mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td

Lines changed: 0 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -425,43 +425,6 @@ def ROCDL_RawPtrBufferAtomicUminOp : ROCDL_RawPtrBufferAtomicNoRet<"umin">;
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// Note: not supported on all architectures
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def ROCDL_RawPtrBufferAtomicFaddOp : ROCDL_RawPtrBufferAtomicNoRet<"fadd">;
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/// LEGACY BUFFER OPERATIONS. DO NOT USE IN NEW CODE. KEPT FOR IR COMPATIBILITY.
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//===---------------------------------------------------------------------===//
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// Vector buffer load/store intrinsics
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def ROCDL_MubufLoadOp :
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ROCDL_Op<"buffer.load">,
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Results<(outs LLVM_Type:$res)>,
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Arguments<(ins LLVM_Type:$rsrc,
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LLVM_Type:$vindex,
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LLVM_Type:$offset,
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LLVM_Type:$glc,
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LLVM_Type:$slc)>{
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string llvmBuilder = [{
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$res = createIntrinsicCall(builder,
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llvm::Intrinsic::amdgcn_buffer_load, {$rsrc, $vindex, $offset, $glc,
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$slc}, {$_resultType});
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}];
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let hasCustomAssemblyFormat = 1;
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}
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def ROCDL_MubufStoreOp :
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ROCDL_Op<"buffer.store">,
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Arguments<(ins LLVM_Type:$vdata,
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LLVM_Type:$rsrc,
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LLVM_Type:$vindex,
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LLVM_Type:$offset,
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LLVM_Type:$glc,
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LLVM_Type:$slc)>{
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string llvmBuilder = [{
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auto vdataType = moduleTranslation.convertType(op.getVdata().getType());
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createIntrinsicCall(builder,
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llvm::Intrinsic::amdgcn_buffer_store, {$vdata, $rsrc, $vindex,
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$offset, $glc, $slc}, {vdataType});
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}];
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let hasCustomAssemblyFormat = 1;
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}
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//===---------------------------------------------------------------------===//
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// Raw buffer load/store intrinsics
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‎mlir/lib/Dialect/LLVMIR/IR/ROCDLDialect.cpp

Lines changed: 0 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -39,54 +39,6 @@ using namespace ROCDL;
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// Parsing for ROCDL ops
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//===----------------------------------------------------------------------===//
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// <operation> ::=
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// `llvm.amdgcn.buffer.load.* %rsrc, %vindex, %offset, %glc, %slc :
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// result_type`
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ParseResult MubufLoadOp::parse(OpAsmParser &parser, OperationState &result) {
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SmallVector<OpAsmParser::UnresolvedOperand, 8> ops;
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Type type;
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if (parser.parseOperandList(ops, 5) || parser.parseColonType(type) ||
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parser.addTypeToList(type, result.types))
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return failure();
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MLIRContext *context = parser.getContext();
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auto int32Ty = IntegerType::get(context, 32);
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auto int1Ty = IntegerType::get(context, 1);
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auto i32x4Ty = LLVM::getFixedVectorType(int32Ty, 4);
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return parser.resolveOperands(ops,
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{i32x4Ty, int32Ty, int32Ty, int1Ty, int1Ty},
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parser.getNameLoc(), result.operands);
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}
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void MubufLoadOp::print(OpAsmPrinter &p) {
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p << " " << getOperands() << " : " << (*this)->getResultTypes();
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}
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// <operation> ::=
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// `llvm.amdgcn.buffer.store.* %vdata, %rsrc, %vindex, %offset, %glc, %slc :
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// result_type`
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ParseResult MubufStoreOp::parse(OpAsmParser &parser, OperationState &result) {
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SmallVector<OpAsmParser::UnresolvedOperand, 8> ops;
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Type type;
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if (parser.parseOperandList(ops, 6) || parser.parseColonType(type))
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return failure();
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MLIRContext *context = parser.getContext();
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auto int32Ty = IntegerType::get(context, 32);
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auto int1Ty = IntegerType::get(context, 1);
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auto i32x4Ty = LLVM::getFixedVectorType(int32Ty, 4);
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if (parser.resolveOperands(ops,
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{type, i32x4Ty, int32Ty, int32Ty, int1Ty, int1Ty},
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parser.getNameLoc(), result.operands))
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return failure();
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return success();
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}
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void MubufStoreOp::print(OpAsmPrinter &p) {
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p << " " << getOperands() << " : " << getVdata().getType();
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}
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// <operation> ::=
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// `llvm.amdgcn.raw.buffer.load.* %rsrc, %offset, %soffset, %aux
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// : result_type`

‎mlir/test/Dialect/LLVMIR/rocdl.mlir

Lines changed: 0 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -273,30 +273,6 @@ llvm.func @rocdl.raw.ptr.buffer.i32(%rsrc : !llvm.ptr<8>,
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// -----
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// Tests for deprecated buffer ops.
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llvm.func @rocdl.mubuf(%rsrc : vector<4xi32>, %vindex : i32,
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%offset : i32, %glc : i1,
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%slc : i1, %vdata1 : vector<1xf32>,
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%vdata2 : vector<2xf32>, %vdata4 : vector<4xf32>) {
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// CHECK-LABEL: rocdl.mubuf
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// CHECK: %{{.*}} = rocdl.buffer.load %{{.*}} %{{.*}} %{{.*}} %{{.*}} %{{.*}} : vector<1xf32>
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%r1 = rocdl.buffer.load %rsrc, %vindex, %offset, %glc, %slc : vector<1xf32>
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// CHECK: %{{.*}} = rocdl.buffer.load %{{.*}} %{{.*}} %{{.*}} %{{.*}} %{{.*}} : vector<2xf32>
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%r2 = rocdl.buffer.load %rsrc, %vindex, %offset, %glc, %slc : vector<2xf32>
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// CHECK: %{{.*}} = rocdl.buffer.load %{{.*}} %{{.*}} %{{.*}} %{{.*}} %{{.*}} : vector<4xf32>
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%r4 = rocdl.buffer.load %rsrc, %vindex, %offset, %glc, %slc : vector<4xf32>
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// CHECK: rocdl.buffer.store %{{.*}} %{{.*}} %{{.*}} %{{.*}} %{{.*}} %{{.*}} : vector<1xf32>
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rocdl.buffer.store %vdata1, %rsrc, %vindex, %offset, %glc, %slc : vector<1xf32>
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// CHECK: rocdl.buffer.store %{{.*}} %{{.*}} %{{.*}} %{{.*}} %{{.*}} %{{.*}} : vector<2xf32>
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rocdl.buffer.store %vdata2, %rsrc, %vindex, %offset, %glc, %slc : vector<2xf32>
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// CHECK: rocdl.buffer.store %{{.*}} %{{.*}} %{{.*}} %{{.*}} %{{.*}} %{{.*}} : vector<4xf32>
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rocdl.buffer.store %vdata4, %rsrc, %vindex, %offset, %glc, %slc : vector<4xf32>
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llvm.return
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}
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llvm.func @rocdl.raw.buffer.f32(%rsrc : vector<4xi32>,
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%offset : i32, %soffset : i32,
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%aux : i32, %vdata1 : f32,

‎mlir/test/Target/LLVMIR/rocdl.mlir

Lines changed: 0 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -429,31 +429,6 @@ llvm.func @rocdl.raw.ptr.buffer.atomic.cmpswap(%rsrc : !llvm.ptr<8>,
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llvm.return %val : i32
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}
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432-
llvm.func @rocdl.mubuf(%rsrc : vector<4xi32>, %vindex : i32,
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%offset : i32, %vdata1 : vector<1xf32>,
434-
%vdata2 : vector<2xf32>, %vdata4 : vector<4xf32>) {
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%glc = llvm.mlir.constant(false) : i1
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%slc = llvm.mlir.constant(true) : i1
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// CHECK-LABEL: rocdl.mubuf
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// CHECK: call <1 x float> @llvm.amdgcn.buffer.load.v1f32(<4 x i32> %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i1 {{.*}}, i1 {{.*}})
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// CHECK: call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i1 {{.*}}, i1 {{.*}})
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// CHECK: call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i1 {{.*}}, i1 {{.*}})
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// CHECK: call void @llvm.amdgcn.buffer.store.v1f32(<1 x float> %{{.*}}, <4 x i32> %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i1 {{.*}}, i1 {{.*}})
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// CHECK: call void @llvm.amdgcn.buffer.store.v2f32(<2 x float> %{{.*}}, <4 x i32> %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i1 {{.*}}, i1 {{.*}})
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// CHECK: call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %{{.*}}, <4 x i32> %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i1 {{.*}}, i1 {{.*}})
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%r1 = rocdl.buffer.load %rsrc, %vindex, %offset, %glc, %slc : vector<1xf32>
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%r2 = rocdl.buffer.load %rsrc, %vindex, %offset, %glc, %slc : vector<2xf32>
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%r4 = rocdl.buffer.load %rsrc, %vindex, %offset, %glc, %slc : vector<4xf32>
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rocdl.buffer.store %vdata1, %rsrc, %vindex, %offset, %glc, %slc : vector<1xf32>
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rocdl.buffer.store %vdata2, %rsrc, %vindex, %offset, %glc, %slc : vector<2xf32>
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rocdl.buffer.store %vdata4, %rsrc, %vindex, %offset, %glc, %slc : vector<4xf32>
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llvm.return
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}
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llvm.func @rocdl.raw.buffer(%rsrc : vector<4xi32>,
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%offset : i32, %soffset : i32,
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%vdata1 : i32,

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