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[CodeGen] Make the parameter TRI required in some functions. (#85968)
Fixes #82659 There are some functions, such as `findRegisterDefOperandIdx` and `findRegisterDefOperand`, that have too many default parameters. As a result, we have encountered some issues due to the lack of TRI parameters, as shown in issue #82411. Following @RKSimon 's suggestion, this patch refactors 9 functions, including `{reads, kills, defines, modifies}Register`, `registerDefIsDead`, and `findRegister{UseOperandIdx, UseOperand, DefOperandIdx, DefOperand}`, adjusting the order of the TRI parameter and making it required. In addition, all the places that call these functions have also been updated correctly to ensure no additional impact. After this, the caller of these functions should explicitly know whether to pass the `TargetRegisterInfo` or just a `nullptr`.
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‎llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -906,7 +906,8 @@ class LegalizationArtifactCombiner {
906906
unsigned &DefOperandIdx) {
907907
if (Register Def = findValueFromDefImpl(Reg, 0, Size)) {
908908
if (auto *Unmerge = dyn_cast<GUnmerge>(MRI.getVRegDef(Def))) {
909-
DefOperandIdx = Unmerge->findRegisterDefOperandIdx(Def);
909+
DefOperandIdx =
910+
Unmerge->findRegisterDefOperandIdx(Def, /*TRI=*/nullptr);
910911
return Unmerge;
911912
}
912913
}

‎llvm/include/llvm/CodeGen/MachineInstr.h

Lines changed: 34 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -1466,9 +1466,8 @@ class MachineInstr
14661466
/// is a read of a super-register.
14671467
/// This does not count partial redefines of virtual registers as reads:
14681468
/// %reg1024:6 = OP.
1469-
bool readsRegister(Register Reg,
1470-
const TargetRegisterInfo *TRI = nullptr) const {
1471-
return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
1469+
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI) const {
1470+
return findRegisterUseOperandIdx(Reg, TRI, false) != -1;
14721471
}
14731472

14741473
/// Return true if the MachineInstr reads the specified virtual register.
@@ -1487,34 +1486,30 @@ class MachineInstr
14871486
/// Return true if the MachineInstr kills the specified register.
14881487
/// If TargetRegisterInfo is non-null, then it also checks if there is
14891488
/// a kill of a super-register.
1490-
bool killsRegister(Register Reg,
1491-
const TargetRegisterInfo *TRI = nullptr) const {
1492-
return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
1489+
bool killsRegister(Register Reg, const TargetRegisterInfo *TRI) const {
1490+
return findRegisterUseOperandIdx(Reg, TRI, true) != -1;
14931491
}
14941492

14951493
/// Return true if the MachineInstr fully defines the specified register.
14961494
/// If TargetRegisterInfo is non-null, then it also checks
14971495
/// if there is a def of a super-register.
14981496
/// NOTE: It's ignoring subreg indices on virtual registers.
1499-
bool definesRegister(Register Reg,
1500-
const TargetRegisterInfo *TRI = nullptr) const {
1501-
return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
1497+
bool definesRegister(Register Reg, const TargetRegisterInfo *TRI) const {
1498+
return findRegisterDefOperandIdx(Reg, TRI, false, false) != -1;
15021499
}
15031500

15041501
/// Return true if the MachineInstr modifies (fully define or partially
15051502
/// define) the specified register.
15061503
/// NOTE: It's ignoring subreg indices on virtual registers.
1507-
bool modifiesRegister(Register Reg,
1508-
const TargetRegisterInfo *TRI = nullptr) const {
1509-
return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
1504+
bool modifiesRegister(Register Reg, const TargetRegisterInfo *TRI) const {
1505+
return findRegisterDefOperandIdx(Reg, TRI, false, true) != -1;
15101506
}
15111507

15121508
/// Returns true if the register is dead in this machine instruction.
15131509
/// If TargetRegisterInfo is non-null, then it also checks
15141510
/// if there is a dead def of a super-register.
1515-
bool registerDefIsDead(Register Reg,
1516-
const TargetRegisterInfo *TRI = nullptr) const {
1517-
return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
1511+
bool registerDefIsDead(Register Reg, const TargetRegisterInfo *TRI) const {
1512+
return findRegisterDefOperandIdx(Reg, TRI, true, false) != -1;
15181513
}
15191514

15201515
/// Returns true if the MachineInstr has an implicit-use operand of exactly
@@ -1524,22 +1519,23 @@ class MachineInstr
15241519
/// Returns the operand index that is a use of the specific register or -1
15251520
/// if it is not found. It further tightens the search criteria to a use
15261521
/// that kills the register if isKill is true.
1527-
int findRegisterUseOperandIdx(Register Reg, bool isKill = false,
1528-
const TargetRegisterInfo *TRI = nullptr) const;
1522+
int findRegisterUseOperandIdx(Register Reg, const TargetRegisterInfo *TRI,
1523+
bool isKill = false) const;
15291524

15301525
/// Wrapper for findRegisterUseOperandIdx, it returns
15311526
/// a pointer to the MachineOperand rather than an index.
1532-
MachineOperand *findRegisterUseOperand(Register Reg, bool isKill = false,
1533-
const TargetRegisterInfo *TRI = nullptr) {
1534-
int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
1527+
MachineOperand *findRegisterUseOperand(Register Reg,
1528+
const TargetRegisterInfo *TRI,
1529+
bool isKill = false) {
1530+
int Idx = findRegisterUseOperandIdx(Reg, TRI, isKill);
15351531
return (Idx == -1) ? nullptr : &getOperand(Idx);
15361532
}
15371533

1538-
const MachineOperand *findRegisterUseOperand(
1539-
Register Reg, bool isKill = false,
1540-
const TargetRegisterInfo *TRI = nullptr) const {
1541-
return const_cast<MachineInstr *>(this)->
1542-
findRegisterUseOperand(Reg, isKill, TRI);
1534+
const MachineOperand *findRegisterUseOperand(Register Reg,
1535+
const TargetRegisterInfo *TRI,
1536+
bool isKill = false) const {
1537+
return const_cast<MachineInstr *>(this)->findRegisterUseOperand(Reg, TRI,
1538+
isKill);
15431539
}
15441540

15451541
/// Returns the operand index that is a def of the specified register or
@@ -1548,26 +1544,26 @@ class MachineInstr
15481544
/// overlap the specified register. If TargetRegisterInfo is non-null,
15491545
/// then it also checks if there is a def of a super-register.
15501546
/// This may also return a register mask operand when Overlap is true.
1551-
int findRegisterDefOperandIdx(Register Reg,
1552-
bool isDead = false, bool Overlap = false,
1553-
const TargetRegisterInfo *TRI = nullptr) const;
1547+
int findRegisterDefOperandIdx(Register Reg, const TargetRegisterInfo *TRI,
1548+
bool isDead = false,
1549+
bool Overlap = false) const;
15541550

15551551
/// Wrapper for findRegisterDefOperandIdx, it returns
15561552
/// a pointer to the MachineOperand rather than an index.
1557-
MachineOperand *
1558-
findRegisterDefOperand(Register Reg, bool isDead = false,
1559-
bool Overlap = false,
1560-
const TargetRegisterInfo *TRI = nullptr) {
1561-
int Idx = findRegisterDefOperandIdx(Reg, isDead, Overlap, TRI);
1553+
MachineOperand *findRegisterDefOperand(Register Reg,
1554+
const TargetRegisterInfo *TRI,
1555+
bool isDead = false,
1556+
bool Overlap = false) {
1557+
int Idx = findRegisterDefOperandIdx(Reg, TRI, isDead, Overlap);
15621558
return (Idx == -1) ? nullptr : &getOperand(Idx);
15631559
}
15641560

1565-
const MachineOperand *
1566-
findRegisterDefOperand(Register Reg, bool isDead = false,
1567-
bool Overlap = false,
1568-
const TargetRegisterInfo *TRI = nullptr) const {
1561+
const MachineOperand *findRegisterDefOperand(Register Reg,
1562+
const TargetRegisterInfo *TRI,
1563+
bool isDead = false,
1564+
bool Overlap = false) const {
15691565
return const_cast<MachineInstr *>(this)->findRegisterDefOperand(
1570-
Reg, isDead, Overlap, TRI);
1566+
Reg, TRI, isDead, Overlap);
15711567
}
15721568

15731569
/// Find the index of the first operand in the

‎llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -231,9 +231,9 @@ bool AggressiveAntiDepBreaker::IsImplicitDefUse(MachineInstr &MI,
231231

232232
MachineOperand *Op = nullptr;
233233
if (MO.isDef())
234-
Op = MI.findRegisterUseOperand(Reg, true);
234+
Op = MI.findRegisterUseOperand(Reg, /*TRI=*/nullptr, true);
235235
else
236-
Op = MI.findRegisterDefOperand(Reg);
236+
Op = MI.findRegisterDefOperand(Reg, /*TRI=*/nullptr);
237237

238238
return(Op && Op->isImplicit());
239239
}
@@ -679,7 +679,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
679679
// defines 'NewReg' via an early-clobber operand.
680680
for (const auto &Q : make_range(RegRefs.equal_range(Reg))) {
681681
MachineInstr *UseMI = Q.second.Operand->getParent();
682-
int Idx = UseMI->findRegisterDefOperandIdx(NewReg, false, true, TRI);
682+
int Idx = UseMI->findRegisterDefOperandIdx(NewReg, TRI, false, true);
683683
if (Idx == -1)
684684
continue;
685685

@@ -846,7 +846,8 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
846846
continue;
847847
} else {
848848
// No anti-dep breaking for implicit deps
849-
MachineOperand *AntiDepOp = MI.findRegisterDefOperand(AntiDepReg);
849+
MachineOperand *AntiDepOp =
850+
MI.findRegisterDefOperand(AntiDepReg, /*TRI=*/nullptr);
850851
assert(AntiDepOp && "Can't find index for defined register operand");
851852
if (!AntiDepOp || AntiDepOp->isImplicit()) {
852853
LLVM_DEBUG(dbgs() << " (implicit)\n");

‎llvm/lib/CodeGen/CalcSpillWeights.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -251,7 +251,8 @@ float VirtRegAuxInfo::weightCalcHelper(LiveInterval &LI, SlotIndex *Start,
251251

252252
// For terminators that produce values, ask the backend if the register is
253253
// not spillable.
254-
if (TII.isUnspillableTerminator(MI) && MI->definesRegister(LI.reg())) {
254+
if (TII.isUnspillableTerminator(MI) &&
255+
MI->definesRegister(LI.reg(), /*TRI=*/nullptr)) {
255256
LI.markNotSpillable();
256257
return -1.0f;
257258
}

‎llvm/lib/CodeGen/CodeGenCommonISel.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -260,7 +260,8 @@ void llvm::salvageDebugInfoForDbgValue(const MachineRegisterInfo &MRI,
260260
continue;
261261
}
262262

263-
int UseMOIdx = DbgMI->findRegisterUseOperandIdx(DefMO->getReg());
263+
int UseMOIdx =
264+
DbgMI->findRegisterUseOperandIdx(DefMO->getReg(), /*TRI=*/nullptr);
264265
assert(UseMOIdx != -1 && DbgMI->hasDebugOperandForReg(DefMO->getReg()) &&
265266
"Must use salvaged instruction as its location");
266267

‎llvm/lib/CodeGen/EarlyIfConversion.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -599,8 +599,8 @@ static bool hasSameValue(const MachineRegisterInfo &MRI,
599599
return false;
600600

601601
// Further, check that the two defs come from corresponding operands.
602-
int TIdx = TDef->findRegisterDefOperandIdx(TReg);
603-
int FIdx = FDef->findRegisterDefOperandIdx(FReg);
602+
int TIdx = TDef->findRegisterDefOperandIdx(TReg, /*TRI=*/nullptr);
603+
int FIdx = FDef->findRegisterDefOperandIdx(FReg, /*TRI=*/nullptr);
604604
if (TIdx == -1 || FIdx == -1)
605605
return false;
606606

‎llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -112,7 +112,7 @@ static Register performCopyPropagation(Register Reg,
112112
bool &IsKill, const TargetInstrInfo &TII,
113113
const TargetRegisterInfo &TRI) {
114114
// First check if statepoint itself uses Reg in non-meta operands.
115-
int Idx = RI->findRegisterUseOperandIdx(Reg, false, &TRI);
115+
int Idx = RI->findRegisterUseOperandIdx(Reg, &TRI, false);
116116
if (Idx >= 0 && (unsigned)Idx < StatepointOpers(&*RI).getNumDeoptArgsIdx()) {
117117
IsKill = false;
118118
return Reg;

‎llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2800,8 +2800,8 @@ bool CombinerHelper::matchEqualDefs(const MachineOperand &MOP1,
28002800
// %5:_(s8), %6:_(s8), %7:_(s8), %8:_(s8) = G_UNMERGE_VALUES %4:_(<4 x s8>)
28012801
// I1 and I2 are different instructions but produce same values,
28022802
// %1 and %6 are same, %1 and %7 are not the same value.
2803-
return I1->findRegisterDefOperandIdx(InstAndDef1->Reg) ==
2804-
I2->findRegisterDefOperandIdx(InstAndDef2->Reg);
2803+
return I1->findRegisterDefOperandIdx(InstAndDef1->Reg, /*TRI=*/nullptr) ==
2804+
I2->findRegisterDefOperandIdx(InstAndDef2->Reg, /*TRI=*/nullptr);
28052805
}
28062806
return false;
28072807
}

‎llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -420,7 +420,8 @@ void RegBankSelect::tryAvoidingSplit(
420420
// If the next terminator uses Reg, this means we have
421421
// to split right after MI and thus we need a way to ask
422422
// which outgoing edges are affected.
423-
assert(!Next->readsRegister(Reg) && "Need to split between terminators");
423+
assert(!Next->readsRegister(Reg, /*TRI=*/nullptr) &&
424+
"Need to split between terminators");
424425
// We will split all the edges and repair there.
425426
} else {
426427
// This is a virtual register defined by a terminator.

‎llvm/lib/CodeGen/InlineSpiller.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -869,7 +869,7 @@ static void dumpMachineInstrRangeWithSlotIndex(MachineBasicBlock::iterator B,
869869
// destination that is marked as an early clobber, print the
870870
// early-clobber slot index.
871871
if (VReg) {
872-
MachineOperand *MO = I->findRegisterDefOperand(VReg);
872+
MachineOperand *MO = I->findRegisterDefOperand(VReg, /*TRI=*/nullptr);
873873
if (MO && MO->isEarlyClobber())
874874
Idx = Idx.getRegSlot(true);
875875
}

‎llvm/lib/CodeGen/LiveVariables.cpp

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -258,7 +258,7 @@ void LiveVariables::HandlePhysRegUse(Register Reg, MachineInstr &MI) {
258258
}
259259
}
260260
} else if (LastDef && !PhysRegUse[Reg] &&
261-
!LastDef->findRegisterDefOperand(Reg))
261+
!LastDef->findRegisterDefOperand(Reg, /*TRI=*/nullptr))
262262
// Last def defines the super register, add an implicit def of reg.
263263
LastDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
264264
true/*IsImp*/));
@@ -361,7 +361,8 @@ bool LiveVariables::HandlePhysRegKill(Register Reg, MachineInstr *MI) {
361361
continue;
362362
bool NeedDef = true;
363363
if (PhysRegDef[Reg] == PhysRegDef[SubReg]) {
364-
MachineOperand *MO = PhysRegDef[Reg]->findRegisterDefOperand(SubReg);
364+
MachineOperand *MO =
365+
PhysRegDef[Reg]->findRegisterDefOperand(SubReg, /*TRI=*/nullptr);
365366
if (MO) {
366367
NeedDef = false;
367368
assert(!MO->isDead());
@@ -388,15 +389,15 @@ bool LiveVariables::HandlePhysRegKill(Register Reg, MachineInstr *MI) {
388389
true/*IsImp*/, true/*IsKill*/));
389390
else {
390391
MachineOperand *MO =
391-
LastRefOrPartRef->findRegisterDefOperand(Reg, false, false, TRI);
392+
LastRefOrPartRef->findRegisterDefOperand(Reg, TRI, false, false);
392393
bool NeedEC = MO->isEarlyClobber() && MO->getReg() != Reg;
393394
// If the last reference is the last def, then it's not used at all.
394395
// That is, unless we are currently processing the last reference itself.
395396
LastRefOrPartRef->addRegisterDead(Reg, TRI, true);
396397
if (NeedEC) {
397398
// If we are adding a subreg def and the superreg def is marked early
398399
// clobber, add an early clobber marker to the subreg def.
399-
MO = LastRefOrPartRef->findRegisterDefOperand(Reg);
400+
MO = LastRefOrPartRef->findRegisterDefOperand(Reg, /*TRI=*/nullptr);
400401
if (MO)
401402
MO->setIsEarlyClobber();
402403
}
@@ -727,7 +728,7 @@ void LiveVariables::recomputeForSingleDefVirtReg(Register Reg) {
727728
if (MI.isPHI())
728729
break;
729730
if (MI.readsVirtualRegister(Reg)) {
730-
assert(!MI.killsRegister(Reg));
731+
assert(!MI.killsRegister(Reg, /*TRI=*/nullptr));
731732
MI.addRegisterKilled(Reg, nullptr);
732733
VI.Kills.push_back(&MI);
733734
break;

‎llvm/lib/CodeGen/MachineCSE.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -709,7 +709,7 @@ bool MachineCSE::ProcessBlockCSE(MachineBasicBlock *MBB) {
709709
for (MachineBasicBlock::iterator II = CSMI, IE = &MI; II != IE; ++II)
710710
for (auto ImplicitDef : ImplicitDefs)
711711
if (MachineOperand *MO = II->findRegisterUseOperand(
712-
ImplicitDef, /*isKill=*/true, TRI))
712+
ImplicitDef, TRI, /*isKill=*/true))
713713
MO->setIsKill(false);
714714
} else {
715715
// If the instructions aren't in the same BB, bail out and clear the

‎llvm/lib/CodeGen/MachineCombiner.cpp

Lines changed: 14 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -229,8 +229,10 @@ MachineCombiner::getDepth(SmallVectorImpl<MachineInstr *> &InsInstrs,
229229
assert(DefInstr &&
230230
"There must be a definition for a new virtual register");
231231
DepthOp = InstrDepth[II->second];
232-
int DefIdx = DefInstr->findRegisterDefOperandIdx(MO.getReg());
233-
int UseIdx = InstrPtr->findRegisterUseOperandIdx(MO.getReg());
232+
int DefIdx =
233+
DefInstr->findRegisterDefOperandIdx(MO.getReg(), /*TRI=*/nullptr);
234+
int UseIdx =
235+
InstrPtr->findRegisterUseOperandIdx(MO.getReg(), /*TRI=*/nullptr);
234236
LatencyOp = TSchedModel.computeOperandLatency(DefInstr, DefIdx,
235237
InstrPtr, UseIdx);
236238
} else {
@@ -241,8 +243,12 @@ MachineCombiner::getDepth(SmallVectorImpl<MachineInstr *> &InsInstrs,
241243
DepthOp = BlockTrace.getInstrCycles(*DefInstr).Depth;
242244
if (!isTransientMI(DefInstr))
243245
LatencyOp = TSchedModel.computeOperandLatency(
244-
DefInstr, DefInstr->findRegisterDefOperandIdx(MO.getReg()),
245-
InstrPtr, InstrPtr->findRegisterUseOperandIdx(MO.getReg()));
246+
DefInstr,
247+
DefInstr->findRegisterDefOperandIdx(MO.getReg(),
248+
/*TRI=*/nullptr),
249+
InstrPtr,
250+
InstrPtr->findRegisterUseOperandIdx(MO.getReg(),
251+
/*TRI=*/nullptr));
246252
}
247253
}
248254
IDepth = std::max(IDepth, DepthOp + LatencyOp);
@@ -280,8 +286,10 @@ unsigned MachineCombiner::getLatency(MachineInstr *Root, MachineInstr *NewRoot,
280286
unsigned LatencyOp = 0;
281287
if (UseMO && BlockTrace.isDepInTrace(*Root, *UseMO)) {
282288
LatencyOp = TSchedModel.computeOperandLatency(
283-
NewRoot, NewRoot->findRegisterDefOperandIdx(MO.getReg()), UseMO,
284-
UseMO->findRegisterUseOperandIdx(MO.getReg()));
289+
NewRoot,
290+
NewRoot->findRegisterDefOperandIdx(MO.getReg(), /*TRI=*/nullptr),
291+
UseMO,
292+
UseMO->findRegisterUseOperandIdx(MO.getReg(), /*TRI=*/nullptr));
285293
} else {
286294
LatencyOp = TSchedModel.computeInstrLatency(NewRoot);
287295
}

‎llvm/lib/CodeGen/MachineCopyPropagation.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -737,7 +737,7 @@ void MachineCopyPropagation::forwardUses(MachineInstr &MI) {
737737
// cannot cope with that.
738738
if (isCopyInstr(MI, *TII, UseCopyInstr) &&
739739
MI.modifiesRegister(CopySrcReg, TRI) &&
740-
!MI.definesRegister(CopySrcReg)) {
740+
!MI.definesRegister(CopySrcReg, /*TRI=*/nullptr)) {
741741
LLVM_DEBUG(dbgs() << "MCP: Copy source overlap with dest in " << MI);
742742
continue;
743743
}

‎llvm/lib/CodeGen/MachineInstr.cpp

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1045,8 +1045,9 @@ bool MachineInstr::hasRegisterImplicitUseOperand(Register Reg) const {
10451045
/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
10461046
/// the specific register or -1 if it is not found. It further tightens
10471047
/// the search criteria to a use that kills the register if isKill is true.
1048-
int MachineInstr::findRegisterUseOperandIdx(
1049-
Register Reg, bool isKill, const TargetRegisterInfo *TRI) const {
1048+
int MachineInstr::findRegisterUseOperandIdx(Register Reg,
1049+
const TargetRegisterInfo *TRI,
1050+
bool isKill) const {
10501051
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
10511052
const MachineOperand &MO = getOperand(i);
10521053
if (!MO.isReg() || !MO.isUse())
@@ -1093,9 +1094,9 @@ MachineInstr::readsWritesVirtualRegister(Register Reg,
10931094
/// the specified register or -1 if it is not found. If isDead is true, defs
10941095
/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
10951096
/// also checks if there is a def of a super-register.
1096-
int
1097-
MachineInstr::findRegisterDefOperandIdx(Register Reg, bool isDead, bool Overlap,
1098-
const TargetRegisterInfo *TRI) const {
1097+
int MachineInstr::findRegisterDefOperandIdx(Register Reg,
1098+
const TargetRegisterInfo *TRI,
1099+
bool isDead, bool Overlap) const {
10991100
bool isPhys = Reg.isPhysical();
11001101
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
11011102
const MachineOperand &MO = getOperand(i);
@@ -2136,7 +2137,7 @@ void MachineInstr::setRegisterDefReadUndef(Register Reg, bool IsUndef) {
21362137
void MachineInstr::addRegisterDefined(Register Reg,
21372138
const TargetRegisterInfo *RegInfo) {
21382139
if (Reg.isPhysical()) {
2139-
MachineOperand *MO = findRegisterDefOperand(Reg, false, false, RegInfo);
2140+
MachineOperand *MO = findRegisterDefOperand(Reg, RegInfo, false, false);
21402141
if (MO)
21412142
return;
21422143
} else {

‎llvm/lib/CodeGen/MachineLateInstrsCleanup.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -230,7 +230,7 @@ bool MachineLateInstrsCleanup::processBlock(MachineBasicBlock *MBB) {
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if (MI.modifiesRegister(Reg, TRI)) {
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MBBDefs.erase(Reg);
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MBBKills.erase(Reg);
233-
} else if (MI.findRegisterUseOperandIdx(Reg, true /*isKill*/, TRI) != -1)
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} else if (MI.findRegisterUseOperandIdx(Reg, TRI, true /*isKill*/) != -1)
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// Keep track of register kills.
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MBBKills[Reg] = &MI;
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}

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