@@ -2985,17 +2985,15 @@ AArch64TargetLowering::EmitZAInstr(unsigned Opc, unsigned BaseReg,
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bool HasZPROut = HasTile && MI.getOperand(0).isReg();
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if (HasZPROut) {
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MIB.add(MI.getOperand(0)); // Output ZPR
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- MIB.addReg(BaseReg + MI.getOperand(1).getImm(),
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- RegState::Define); // Output ZA Tile
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- MIB.addReg(BaseReg + MI.getOperand(1).getImm()); // Input Za Tile
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- StartIdx = 2;
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+ ++StartIdx;
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+ }
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+ if (HasTile) {
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+ MIB.addReg(BaseReg + MI.getOperand(StartIdx).getImm(),
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+ RegState::Define); // Output ZA Tile
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+ MIB.addReg(BaseReg + MI.getOperand(StartIdx).getImm()); // Input Za Tile
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+ StartIdx++;
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} else {
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- if (HasTile) {
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- MIB.addReg(BaseReg + MI.getOperand(0).getImm(), RegState::Define);
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- MIB.addReg(BaseReg + MI.getOperand(0).getImm());
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- StartIdx = 1;
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- } else
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- MIB.addReg(BaseReg, RegState::Define).addReg(BaseReg);
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+ MIB.addReg(BaseReg, RegState::Define).addReg(BaseReg);
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}
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for (unsigned I = StartIdx; I < MI.getNumOperands(); ++I)
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MIB.add(MI.getOperand(I));
@@ -3110,7 +3108,6 @@ MachineBasicBlock *AArch64TargetLowering::EmitInstrWithCustomInserter(
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return EmitZAInstr(SMEOrigInstr, AArch64::ZAB0, MI, BB);
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case (AArch64::SMEMatrixTileH):
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return EmitZAInstr(SMEOrigInstr, AArch64::ZAH0, MI, BB);
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- ///*HasTile*/ true, /*HasZPROut*/ false);
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case (AArch64::SMEMatrixTileS):
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return EmitZAInstr(SMEOrigInstr, AArch64::ZAS0, MI, BB);
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case (AArch64::SMEMatrixTileD):
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