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Revert "[AArch64] Combine and and lsl into ubfiz" (#123356)
Reverts #118974
1 parent c531255 commit f719771

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5 files changed

+65
-115
lines changed

5 files changed

+65
-115
lines changed

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 0 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -1140,8 +1140,6 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
11401140

11411141
setTargetDAGCombine(ISD::SCALAR_TO_VECTOR);
11421142

1143-
setTargetDAGCombine(ISD::SHL);
1144-
11451143
// In case of strict alignment, avoid an excessive number of byte wide stores.
11461144
MaxStoresPerMemsetOptSize = 8;
11471145
MaxStoresPerMemset =
@@ -26474,43 +26472,6 @@ performScalarToVectorCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
2647426472
return NVCAST;
2647526473
}
2647626474

26477-
/// If the operand is a bitwise AND with a constant RHS, and the shift has a
26478-
/// constant RHS and is the only use, we can pull it out of the shift, i.e.
26479-
///
26480-
/// (shl (and X, C1), C2) -> (and (shl X, C2), (shl C1, C2))
26481-
///
26482-
/// We prefer this canonical form to match existing isel patterns.
26483-
static SDValue performSHLCombine(SDNode *N,
26484-
TargetLowering::DAGCombinerInfo &DCI,
26485-
SelectionDAG &DAG) {
26486-
if (DCI.isBeforeLegalizeOps())
26487-
return SDValue();
26488-
26489-
SDValue Op0 = N->getOperand(0);
26490-
if (Op0.getOpcode() != ISD::AND || !Op0.hasOneUse())
26491-
return SDValue();
26492-
26493-
SDValue C1 = Op0->getOperand(1);
26494-
SDValue C2 = N->getOperand(1);
26495-
if (!isa<ConstantSDNode>(C1) || !isa<ConstantSDNode>(C2))
26496-
return SDValue();
26497-
26498-
// Might be folded into shifted op, do not lower.
26499-
if (N->hasOneUse()) {
26500-
unsigned UseOpc = N->user_begin()->getOpcode();
26501-
if (UseOpc == ISD::ADD || UseOpc == ISD::SUB || UseOpc == ISD::SETCC ||
26502-
UseOpc == AArch64ISD::ADDS || UseOpc == AArch64ISD::SUBS)
26503-
return SDValue();
26504-
}
26505-
26506-
SDLoc DL(N);
26507-
EVT VT = N->getValueType(0);
26508-
SDValue X = Op0->getOperand(0);
26509-
SDValue NewRHS = DAG.getNode(ISD::SHL, DL, VT, C1, C2);
26510-
SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, X, C2);
26511-
return DAG.getNode(ISD::AND, DL, VT, NewShift, NewRHS);
26512-
}
26513-
2651426475
SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
2651526476
DAGCombinerInfo &DCI) const {
2651626477
SelectionDAG &DAG = DCI.DAG;
@@ -26856,8 +26817,6 @@ SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
2685626817
return performCTLZCombine(N, DAG, Subtarget);
2685726818
case ISD::SCALAR_TO_VECTOR:
2685826819
return performScalarToVectorCombine(N, DCI, DAG);
26859-
case ISD::SHL:
26860-
return performSHLCombine(N, DCI, DAG);
2686126820
}
2686226821
return SDValue();
2686326822
}

‎llvm/test/CodeGen/AArch64/const-shift-of-constmasked.ll

Lines changed: 54 additions & 47 deletions
Original file line numberDiff line numberDiff line change
@@ -190,7 +190,8 @@ define i8 @test_i8_224_mask_ashr_6(i8 %a0) {
190190
define i8 @test_i8_7_mask_shl_1(i8 %a0) {
191191
; CHECK-LABEL: test_i8_7_mask_shl_1:
192192
; CHECK: // %bb.0:
193-
; CHECK-NEXT: ubfiz w0, w0, #1, #3
193+
; CHECK-NEXT: and w8, w0, #0x7
194+
; CHECK-NEXT: lsl w0, w8, #1
194195
; CHECK-NEXT: ret
195196
%t0 = and i8 %a0, 7
196197
%t1 = shl i8 %t0, 1
@@ -199,7 +200,8 @@ define i8 @test_i8_7_mask_shl_1(i8 %a0) {
199200
define i8 @test_i8_7_mask_shl_4(i8 %a0) {
200201
; CHECK-LABEL: test_i8_7_mask_shl_4:
201202
; CHECK: // %bb.0:
202-
; CHECK-NEXT: ubfiz w0, w0, #4, #3
203+
; CHECK-NEXT: and w8, w0, #0x7
204+
; CHECK-NEXT: lsl w0, w8, #4
203205
; CHECK-NEXT: ret
204206
%t0 = and i8 %a0, 7
205207
%t1 = shl i8 %t0, 4
@@ -227,8 +229,8 @@ define i8 @test_i8_7_mask_shl_6(i8 %a0) {
227229
define i8 @test_i8_28_mask_shl_1(i8 %a0) {
228230
; CHECK-LABEL: test_i8_28_mask_shl_1:
229231
; CHECK: // %bb.0:
230-
; CHECK-NEXT: lsl w8, w0, #1
231-
; CHECK-NEXT: and w0, w8, #0x38
232+
; CHECK-NEXT: and w8, w0, #0x1c
233+
; CHECK-NEXT: lsl w0, w8, #1
232234
; CHECK-NEXT: ret
233235
%t0 = and i8 %a0, 28
234236
%t1 = shl i8 %t0, 1
@@ -237,8 +239,8 @@ define i8 @test_i8_28_mask_shl_1(i8 %a0) {
237239
define i8 @test_i8_28_mask_shl_2(i8 %a0) {
238240
; CHECK-LABEL: test_i8_28_mask_shl_2:
239241
; CHECK: // %bb.0:
240-
; CHECK-NEXT: lsl w8, w0, #2
241-
; CHECK-NEXT: and w0, w8, #0x70
242+
; CHECK-NEXT: and w8, w0, #0x1c
243+
; CHECK-NEXT: lsl w0, w8, #2
242244
; CHECK-NEXT: ret
243245
%t0 = and i8 %a0, 28
244246
%t1 = shl i8 %t0, 2
@@ -247,8 +249,8 @@ define i8 @test_i8_28_mask_shl_2(i8 %a0) {
247249
define i8 @test_i8_28_mask_shl_3(i8 %a0) {
248250
; CHECK-LABEL: test_i8_28_mask_shl_3:
249251
; CHECK: // %bb.0:
250-
; CHECK-NEXT: lsl w8, w0, #3
251-
; CHECK-NEXT: and w0, w8, #0xe0
252+
; CHECK-NEXT: and w8, w0, #0x1c
253+
; CHECK-NEXT: lsl w0, w8, #3
252254
; CHECK-NEXT: ret
253255
%t0 = and i8 %a0, 28
254256
%t1 = shl i8 %t0, 3
@@ -257,8 +259,8 @@ define i8 @test_i8_28_mask_shl_3(i8 %a0) {
257259
define i8 @test_i8_28_mask_shl_4(i8 %a0) {
258260
; CHECK-LABEL: test_i8_28_mask_shl_4:
259261
; CHECK: // %bb.0:
260-
; CHECK-NEXT: lsl w8, w0, #4
261-
; CHECK-NEXT: and w0, w8, #0xc0
262+
; CHECK-NEXT: and w8, w0, #0xc
263+
; CHECK-NEXT: lsl w0, w8, #4
262264
; CHECK-NEXT: ret
263265
%t0 = and i8 %a0, 28
264266
%t1 = shl i8 %t0, 4
@@ -268,8 +270,8 @@ define i8 @test_i8_28_mask_shl_4(i8 %a0) {
268270
define i8 @test_i8_224_mask_shl_1(i8 %a0) {
269271
; CHECK-LABEL: test_i8_224_mask_shl_1:
270272
; CHECK: // %bb.0:
271-
; CHECK-NEXT: lsl w8, w0, #1
272-
; CHECK-NEXT: and w0, w8, #0xc0
273+
; CHECK-NEXT: and w8, w0, #0x60
274+
; CHECK-NEXT: lsl w0, w8, #1
273275
; CHECK-NEXT: ret
274276
%t0 = and i8 %a0, 224
275277
%t1 = shl i8 %t0, 1
@@ -463,7 +465,8 @@ define i16 @test_i16_65024_mask_ashr_10(i16 %a0) {
463465
define i16 @test_i16_127_mask_shl_1(i16 %a0) {
464466
; CHECK-LABEL: test_i16_127_mask_shl_1:
465467
; CHECK: // %bb.0:
466-
; CHECK-NEXT: ubfiz w0, w0, #1, #7
468+
; CHECK-NEXT: and w8, w0, #0x7f
469+
; CHECK-NEXT: lsl w0, w8, #1
467470
; CHECK-NEXT: ret
468471
%t0 = and i16 %a0, 127
469472
%t1 = shl i16 %t0, 1
@@ -472,7 +475,8 @@ define i16 @test_i16_127_mask_shl_1(i16 %a0) {
472475
define i16 @test_i16_127_mask_shl_8(i16 %a0) {
473476
; CHECK-LABEL: test_i16_127_mask_shl_8:
474477
; CHECK: // %bb.0:
475-
; CHECK-NEXT: ubfiz w0, w0, #8, #7
478+
; CHECK-NEXT: and w8, w0, #0x7f
479+
; CHECK-NEXT: lsl w0, w8, #8
476480
; CHECK-NEXT: ret
477481
%t0 = and i16 %a0, 127
478482
%t1 = shl i16 %t0, 8
@@ -500,8 +504,8 @@ define i16 @test_i16_127_mask_shl_10(i16 %a0) {
500504
define i16 @test_i16_2032_mask_shl_3(i16 %a0) {
501505
; CHECK-LABEL: test_i16_2032_mask_shl_3:
502506
; CHECK: // %bb.0:
503-
; CHECK-NEXT: lsl w8, w0, #3
504-
; CHECK-NEXT: and w0, w8, #0x3f80
507+
; CHECK-NEXT: and w8, w0, #0x7f0
508+
; CHECK-NEXT: lsl w0, w8, #3
505509
; CHECK-NEXT: ret
506510
%t0 = and i16 %a0, 2032
507511
%t1 = shl i16 %t0, 3
@@ -510,8 +514,8 @@ define i16 @test_i16_2032_mask_shl_3(i16 %a0) {
510514
define i16 @test_i16_2032_mask_shl_4(i16 %a0) {
511515
; CHECK-LABEL: test_i16_2032_mask_shl_4:
512516
; CHECK: // %bb.0:
513-
; CHECK-NEXT: lsl w8, w0, #4
514-
; CHECK-NEXT: and w0, w8, #0x7f00
517+
; CHECK-NEXT: and w8, w0, #0x7f0
518+
; CHECK-NEXT: lsl w0, w8, #4
515519
; CHECK-NEXT: ret
516520
%t0 = and i16 %a0, 2032
517521
%t1 = shl i16 %t0, 4
@@ -520,8 +524,8 @@ define i16 @test_i16_2032_mask_shl_4(i16 %a0) {
520524
define i16 @test_i16_2032_mask_shl_5(i16 %a0) {
521525
; CHECK-LABEL: test_i16_2032_mask_shl_5:
522526
; CHECK: // %bb.0:
523-
; CHECK-NEXT: lsl w8, w0, #5
524-
; CHECK-NEXT: and w0, w8, #0xfe00
527+
; CHECK-NEXT: and w8, w0, #0x7f0
528+
; CHECK-NEXT: lsl w0, w8, #5
525529
; CHECK-NEXT: ret
526530
%t0 = and i16 %a0, 2032
527531
%t1 = shl i16 %t0, 5
@@ -530,8 +534,8 @@ define i16 @test_i16_2032_mask_shl_5(i16 %a0) {
530534
define i16 @test_i16_2032_mask_shl_6(i16 %a0) {
531535
; CHECK-LABEL: test_i16_2032_mask_shl_6:
532536
; CHECK: // %bb.0:
533-
; CHECK-NEXT: lsl w8, w0, #6
534-
; CHECK-NEXT: and w0, w8, #0xfc00
537+
; CHECK-NEXT: and w8, w0, #0x3f0
538+
; CHECK-NEXT: lsl w0, w8, #6
535539
; CHECK-NEXT: ret
536540
%t0 = and i16 %a0, 2032
537541
%t1 = shl i16 %t0, 6
@@ -541,8 +545,8 @@ define i16 @test_i16_2032_mask_shl_6(i16 %a0) {
541545
define i16 @test_i16_65024_mask_shl_1(i16 %a0) {
542546
; CHECK-LABEL: test_i16_65024_mask_shl_1:
543547
; CHECK: // %bb.0:
544-
; CHECK-NEXT: lsl w8, w0, #1
545-
; CHECK-NEXT: and w0, w8, #0xfc00
548+
; CHECK-NEXT: and w8, w0, #0x7e00
549+
; CHECK-NEXT: lsl w0, w8, #1
546550
; CHECK-NEXT: ret
547551
%t0 = and i16 %a0, 65024
548552
%t1 = shl i16 %t0, 1
@@ -736,7 +740,8 @@ define i32 @test_i32_4294836224_mask_ashr_18(i32 %a0) {
736740
define i32 @test_i32_32767_mask_shl_1(i32 %a0) {
737741
; CHECK-LABEL: test_i32_32767_mask_shl_1:
738742
; CHECK: // %bb.0:
739-
; CHECK-NEXT: ubfiz w0, w0, #1, #15
743+
; CHECK-NEXT: and w8, w0, #0x7fff
744+
; CHECK-NEXT: lsl w0, w8, #1
740745
; CHECK-NEXT: ret
741746
%t0 = and i32 %a0, 32767
742747
%t1 = shl i32 %t0, 1
@@ -745,7 +750,8 @@ define i32 @test_i32_32767_mask_shl_1(i32 %a0) {
745750
define i32 @test_i32_32767_mask_shl_16(i32 %a0) {
746751
; CHECK-LABEL: test_i32_32767_mask_shl_16:
747752
; CHECK: // %bb.0:
748-
; CHECK-NEXT: ubfiz w0, w0, #16, #15
753+
; CHECK-NEXT: and w8, w0, #0x7fff
754+
; CHECK-NEXT: lsl w0, w8, #16
749755
; CHECK-NEXT: ret
750756
%t0 = and i32 %a0, 32767
751757
%t1 = shl i32 %t0, 16
@@ -773,8 +779,8 @@ define i32 @test_i32_32767_mask_shl_18(i32 %a0) {
773779
define i32 @test_i32_8388352_mask_shl_7(i32 %a0) {
774780
; CHECK-LABEL: test_i32_8388352_mask_shl_7:
775781
; CHECK: // %bb.0:
776-
; CHECK-NEXT: lsl w8, w0, #7
777-
; CHECK-NEXT: and w0, w8, #0x3fff8000
782+
; CHECK-NEXT: and w8, w0, #0x7fff00
783+
; CHECK-NEXT: lsl w0, w8, #7
778784
; CHECK-NEXT: ret
779785
%t0 = and i32 %a0, 8388352
780786
%t1 = shl i32 %t0, 7
@@ -783,8 +789,8 @@ define i32 @test_i32_8388352_mask_shl_7(i32 %a0) {
783789
define i32 @test_i32_8388352_mask_shl_8(i32 %a0) {
784790
; CHECK-LABEL: test_i32_8388352_mask_shl_8:
785791
; CHECK: // %bb.0:
786-
; CHECK-NEXT: lsl w8, w0, #8
787-
; CHECK-NEXT: and w0, w8, #0x7fff0000
792+
; CHECK-NEXT: and w8, w0, #0x7fff00
793+
; CHECK-NEXT: lsl w0, w8, #8
788794
; CHECK-NEXT: ret
789795
%t0 = and i32 %a0, 8388352
790796
%t1 = shl i32 %t0, 8
@@ -793,8 +799,8 @@ define i32 @test_i32_8388352_mask_shl_8(i32 %a0) {
793799
define i32 @test_i32_8388352_mask_shl_9(i32 %a0) {
794800
; CHECK-LABEL: test_i32_8388352_mask_shl_9:
795801
; CHECK: // %bb.0:
796-
; CHECK-NEXT: lsl w8, w0, #9
797-
; CHECK-NEXT: and w0, w8, #0xfffe0000
802+
; CHECK-NEXT: and w8, w0, #0x7fff00
803+
; CHECK-NEXT: lsl w0, w8, #9
798804
; CHECK-NEXT: ret
799805
%t0 = and i32 %a0, 8388352
800806
%t1 = shl i32 %t0, 9
@@ -803,8 +809,8 @@ define i32 @test_i32_8388352_mask_shl_9(i32 %a0) {
803809
define i32 @test_i32_8388352_mask_shl_10(i32 %a0) {
804810
; CHECK-LABEL: test_i32_8388352_mask_shl_10:
805811
; CHECK: // %bb.0:
806-
; CHECK-NEXT: lsl w8, w0, #10
807-
; CHECK-NEXT: and w0, w8, #0xfffc0000
812+
; CHECK-NEXT: and w8, w0, #0x3fff00
813+
; CHECK-NEXT: lsl w0, w8, #10
808814
; CHECK-NEXT: ret
809815
%t0 = and i32 %a0, 8388352
810816
%t1 = shl i32 %t0, 10
@@ -814,8 +820,8 @@ define i32 @test_i32_8388352_mask_shl_10(i32 %a0) {
814820
define i32 @test_i32_4294836224_mask_shl_1(i32 %a0) {
815821
; CHECK-LABEL: test_i32_4294836224_mask_shl_1:
816822
; CHECK: // %bb.0:
817-
; CHECK-NEXT: lsl w8, w0, #1
818-
; CHECK-NEXT: and w0, w8, #0xfffc0000
823+
; CHECK-NEXT: and w8, w0, #0x7ffe0000
824+
; CHECK-NEXT: lsl w0, w8, #1
819825
; CHECK-NEXT: ret
820826
%t0 = and i32 %a0, 4294836224
821827
%t1 = shl i32 %t0, 1
@@ -1009,7 +1015,8 @@ define i64 @test_i64_18446744065119617024_mask_ashr_34(i64 %a0) {
10091015
define i64 @test_i64_2147483647_mask_shl_1(i64 %a0) {
10101016
; CHECK-LABEL: test_i64_2147483647_mask_shl_1:
10111017
; CHECK: // %bb.0:
1012-
; CHECK-NEXT: lsl w0, w0, #1
1018+
; CHECK-NEXT: and x8, x0, #0x7fffffff
1019+
; CHECK-NEXT: lsl x0, x8, #1
10131020
; CHECK-NEXT: ret
10141021
%t0 = and i64 %a0, 2147483647
10151022
%t1 = shl i64 %t0, 1
@@ -1047,8 +1054,8 @@ define i64 @test_i64_2147483647_mask_shl_34(i64 %a0) {
10471054
define i64 @test_i64_140737488289792_mask_shl_15(i64 %a0) {
10481055
; CHECK-LABEL: test_i64_140737488289792_mask_shl_15:
10491056
; CHECK: // %bb.0:
1050-
; CHECK-NEXT: lsl x8, x0, #15
1051-
; CHECK-NEXT: and x0, x8, #0x3fffffff80000000
1057+
; CHECK-NEXT: and x8, x0, #0x7fffffff0000
1058+
; CHECK-NEXT: lsl x0, x8, #15
10521059
; CHECK-NEXT: ret
10531060
%t0 = and i64 %a0, 140737488289792
10541061
%t1 = shl i64 %t0, 15
@@ -1057,8 +1064,8 @@ define i64 @test_i64_140737488289792_mask_shl_15(i64 %a0) {
10571064
define i64 @test_i64_140737488289792_mask_shl_16(i64 %a0) {
10581065
; CHECK-LABEL: test_i64_140737488289792_mask_shl_16:
10591066
; CHECK: // %bb.0:
1060-
; CHECK-NEXT: lsl x8, x0, #16
1061-
; CHECK-NEXT: and x0, x8, #0x7fffffff00000000
1067+
; CHECK-NEXT: and x8, x0, #0x7fffffff0000
1068+
; CHECK-NEXT: lsl x0, x8, #16
10621069
; CHECK-NEXT: ret
10631070
%t0 = and i64 %a0, 140737488289792
10641071
%t1 = shl i64 %t0, 16
@@ -1067,8 +1074,8 @@ define i64 @test_i64_140737488289792_mask_shl_16(i64 %a0) {
10671074
define i64 @test_i64_140737488289792_mask_shl_17(i64 %a0) {
10681075
; CHECK-LABEL: test_i64_140737488289792_mask_shl_17:
10691076
; CHECK: // %bb.0:
1070-
; CHECK-NEXT: lsl x8, x0, #17
1071-
; CHECK-NEXT: and x0, x8, #0xfffffffe00000000
1077+
; CHECK-NEXT: and x8, x0, #0x7fffffff0000
1078+
; CHECK-NEXT: lsl x0, x8, #17
10721079
; CHECK-NEXT: ret
10731080
%t0 = and i64 %a0, 140737488289792
10741081
%t1 = shl i64 %t0, 17
@@ -1077,8 +1084,8 @@ define i64 @test_i64_140737488289792_mask_shl_17(i64 %a0) {
10771084
define i64 @test_i64_140737488289792_mask_shl_18(i64 %a0) {
10781085
; CHECK-LABEL: test_i64_140737488289792_mask_shl_18:
10791086
; CHECK: // %bb.0:
1080-
; CHECK-NEXT: lsl x8, x0, #18
1081-
; CHECK-NEXT: and x0, x8, #0xfffffffc00000000
1087+
; CHECK-NEXT: and x8, x0, #0x3fffffff0000
1088+
; CHECK-NEXT: lsl x0, x8, #18
10821089
; CHECK-NEXT: ret
10831090
%t0 = and i64 %a0, 140737488289792
10841091
%t1 = shl i64 %t0, 18
@@ -1088,8 +1095,8 @@ define i64 @test_i64_140737488289792_mask_shl_18(i64 %a0) {
10881095
define i64 @test_i64_18446744065119617024_mask_shl_1(i64 %a0) {
10891096
; CHECK-LABEL: test_i64_18446744065119617024_mask_shl_1:
10901097
; CHECK: // %bb.0:
1091-
; CHECK-NEXT: lsl x8, x0, #1
1092-
; CHECK-NEXT: and x0, x8, #0xfffffffc00000000
1098+
; CHECK-NEXT: and x8, x0, #0x7ffffffe00000000
1099+
; CHECK-NEXT: lsl x0, x8, #1
10931100
; CHECK-NEXT: ret
10941101
%t0 = and i64 %a0, 18446744065119617024
10951102
%t1 = shl i64 %t0, 1

‎llvm/test/CodeGen/AArch64/extract-bits.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1013,8 +1013,8 @@ define i32 @c1_i32(i32 %arg) nounwind {
10131013
define i32 @c2_i32(i32 %arg) nounwind {
10141014
; CHECK-LABEL: c2_i32:
10151015
; CHECK: // %bb.0:
1016-
; CHECK-NEXT: lsr w8, w0, #17
1017-
; CHECK-NEXT: and w0, w8, #0xffc
1016+
; CHECK-NEXT: ubfx w8, w0, #19, #10
1017+
; CHECK-NEXT: lsl w0, w8, #2
10181018
; CHECK-NEXT: ret
10191019
%tmp0 = lshr i32 %arg, 19
10201020
%tmp1 = and i32 %tmp0, 1023
@@ -1063,8 +1063,8 @@ define i64 @c1_i64(i64 %arg) nounwind {
10631063
define i64 @c2_i64(i64 %arg) nounwind {
10641064
; CHECK-LABEL: c2_i64:
10651065
; CHECK: // %bb.0:
1066-
; CHECK-NEXT: lsr x8, x0, #49
1067-
; CHECK-NEXT: and x0, x8, #0xffc
1066+
; CHECK-NEXT: ubfx x8, x0, #51, #10
1067+
; CHECK-NEXT: lsl x0, x8, #2
10681068
; CHECK-NEXT: ret
10691069
%tmp0 = lshr i64 %arg, 51
10701070
%tmp1 = and i64 %tmp0, 1023
@@ -1120,8 +1120,8 @@ define void @c6_i32(i32 %arg, ptr %ptr) nounwind {
11201120
define void @c7_i32(i32 %arg, ptr %ptr) nounwind {
11211121
; CHECK-LABEL: c7_i32:
11221122
; CHECK: // %bb.0:
1123-
; CHECK-NEXT: lsr w8, w0, #17
1124-
; CHECK-NEXT: and w8, w8, #0xffc
1123+
; CHECK-NEXT: ubfx w8, w0, #19, #10
1124+
; CHECK-NEXT: lsl w8, w8, #2
11251125
; CHECK-NEXT: str w8, [x1]
11261126
; CHECK-NEXT: ret
11271127
%tmp0 = lshr i32 %arg, 19
@@ -1163,8 +1163,8 @@ define void @c6_i64(i64 %arg, ptr %ptr) nounwind {
11631163
define void @c7_i64(i64 %arg, ptr %ptr) nounwind {
11641164
; CHECK-LABEL: c7_i64:
11651165
; CHECK: // %bb.0:
1166-
; CHECK-NEXT: lsr x8, x0, #49
1167-
; CHECK-NEXT: and x8, x8, #0xffc
1166+
; CHECK-NEXT: ubfx x8, x0, #51, #10
1167+
; CHECK-NEXT: lsl x8, x8, #2
11681168
; CHECK-NEXT: str x8, [x1]
11691169
; CHECK-NEXT: ret
11701170
%tmp0 = lshr i64 %arg, 51

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