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[SelectionDAG] Use getShiftAmountConstant to simplify code. NFC (#80561)
Replace calls to getShiftAmountTy+getConstant with getShiftAmountContant.
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‎llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Lines changed: 44 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -1096,7 +1096,6 @@ bool TargetLowering::SimplifyDemandedBits(
10961096
APInt DemandedBits = OriginalDemandedBits;
10971097
APInt DemandedElts = OriginalDemandedElts;
10981098
SDLoc dl(Op);
1099-
auto &DL = TLO.DAG.getDataLayout();
11001099

11011100
// Undef operand.
11021101
if (Op.isUndef())
@@ -2288,9 +2287,8 @@ bool TargetLowering::SimplifyDemandedBits(
22882287
// the right place.
22892288
unsigned ShiftOpcode = NLZ > NTZ ? ISD::SRL : ISD::SHL;
22902289
if (!TLO.LegalOperations() || isOperationLegal(ShiftOpcode, VT)) {
2291-
EVT ShiftAmtTy = getShiftAmountTy(VT, DL);
22922290
unsigned ShiftAmount = NLZ > NTZ ? NLZ - NTZ : NTZ - NLZ;
2293-
SDValue ShAmt = TLO.DAG.getConstant(ShiftAmount, dl, ShiftAmtTy);
2291+
SDValue ShAmt = TLO.DAG.getShiftAmountConstant(ShiftAmount, VT, dl);
22942292
SDValue NewOp = TLO.DAG.getNode(ShiftOpcode, dl, VT, Src, ShAmt);
22952293
return TLO.CombineTo(Op, NewOp);
22962294
}
@@ -2330,8 +2328,8 @@ bool TargetLowering::SimplifyDemandedBits(
23302328
if (!AlreadySignExtended) {
23312329
// Compute the correct shift amount type, which must be getShiftAmountTy
23322330
// for scalar types after legalization.
2333-
SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ExVTBits, dl,
2334-
getShiftAmountTy(VT, DL));
2331+
SDValue ShiftAmt =
2332+
TLO.DAG.getShiftAmountConstant(BitWidth - ExVTBits, VT, dl);
23352333
return TLO.CombineTo(Op,
23362334
TLO.DAG.getNode(ISD::SHL, dl, VT, Op0, ShiftAmt));
23372335
}
@@ -2574,8 +2572,8 @@ bool TargetLowering::SimplifyDemandedBits(
25742572
if (!(HighBits & DemandedBits)) {
25752573
// None of the shifted in bits are needed. Add a truncate of the
25762574
// shift input, then shift it.
2577-
SDValue NewShAmt = TLO.DAG.getConstant(
2578-
ShVal, dl, getShiftAmountTy(VT, DL, TLO.LegalTypes()));
2575+
SDValue NewShAmt =
2576+
TLO.DAG.getShiftAmountConstant(ShVal, VT, dl, TLO.LegalTypes());
25792577
SDValue NewTrunc =
25802578
TLO.DAG.getNode(ISD::TRUNCATE, dl, VT, Src.getOperand(0));
25812579
return TLO.CombineTo(
@@ -2753,8 +2751,7 @@ bool TargetLowering::SimplifyDemandedBits(
27532751
unsigned CTZ = DemandedBits.countr_zero();
27542752
ConstantSDNode *C = isConstOrConstSplat(Op.getOperand(1), DemandedElts);
27552753
if (C && C->getAPIntValue().countr_zero() == CTZ) {
2756-
EVT ShiftAmtTy = getShiftAmountTy(VT, TLO.DAG.getDataLayout());
2757-
SDValue AmtC = TLO.DAG.getConstant(CTZ, dl, ShiftAmtTy);
2754+
SDValue AmtC = TLO.DAG.getShiftAmountConstant(CTZ, VT, dl);
27582755
SDValue Shl = TLO.DAG.getNode(ISD::SHL, dl, VT, Op.getOperand(0), AmtC);
27592756
return TLO.CombineTo(Op, Shl);
27602757
}
@@ -2852,9 +2849,9 @@ bool TargetLowering::SimplifyDemandedBits(
28522849
return 0;
28532850
};
28542851

2855-
auto foldMul = [&](ISD::NodeType NT, SDValue X, SDValue Y, unsigned ShlAmt) {
2856-
EVT ShiftAmtTy = getShiftAmountTy(VT, TLO.DAG.getDataLayout());
2857-
SDValue ShlAmtC = TLO.DAG.getConstant(ShlAmt, dl, ShiftAmtTy);
2852+
auto foldMul = [&](ISD::NodeType NT, SDValue X, SDValue Y,
2853+
unsigned ShlAmt) {
2854+
SDValue ShlAmtC = TLO.DAG.getShiftAmountConstant(ShlAmt, VT, dl);
28582855
SDValue Shl = TLO.DAG.getNode(ISD::SHL, dl, VT, X, ShlAmtC);
28592856
SDValue Res = TLO.DAG.getNode(NT, dl, VT, Y, Shl);
28602857
return TLO.CombineTo(Op, Res);
@@ -4204,9 +4201,8 @@ SDValue TargetLowering::foldSetCCWithBinOp(EVT VT, SDValue N0, SDValue N1,
42044201
return SDValue();
42054202

42064203
// (X - Y) == Y --> X == Y << 1
4207-
EVT ShiftVT = getShiftAmountTy(OpVT, DAG.getDataLayout(),
4208-
!DCI.isBeforeLegalize());
4209-
SDValue One = DAG.getConstant(1, DL, ShiftVT);
4204+
SDValue One =
4205+
DAG.getShiftAmountConstant(1, OpVT, DL, !DCI.isBeforeLegalize());
42104206
SDValue YShl1 = DAG.getNode(ISD::SHL, DL, N1.getValueType(), Y, One);
42114207
if (!DCI.isCalledByLegalizer())
42124208
DCI.AddToWorklist(YShl1.getNode());
@@ -5038,34 +5034,35 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
50385034
(VT == ShValTy || (isTypeLegal(VT) && VT.bitsLE(ShValTy))) &&
50395035
N0.getOpcode() == ISD::AND) {
50405036
if (auto *AndRHS = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
5041-
EVT ShiftTy =
5042-
getShiftAmountTy(ShValTy, Layout, !DCI.isBeforeLegalize());
50435037
if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
50445038
// Perform the xform if the AND RHS is a single bit.
50455039
unsigned ShCt = AndRHS->getAPIntValue().logBase2();
50465040
if (AndRHS->getAPIntValue().isPowerOf2() &&
50475041
!TLI.shouldAvoidTransformToShift(ShValTy, ShCt)) {
5048-
return DAG.getNode(ISD::TRUNCATE, dl, VT,
5049-
DAG.getNode(ISD::SRL, dl, ShValTy, N0,
5050-
DAG.getConstant(ShCt, dl, ShiftTy)));
5042+
return DAG.getNode(
5043+
ISD::TRUNCATE, dl, VT,
5044+
DAG.getNode(ISD::SRL, dl, ShValTy, N0,
5045+
DAG.getShiftAmountConstant(
5046+
ShCt, ShValTy, dl, !DCI.isBeforeLegalize())));
50515047
}
50525048
} else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
50535049
// (X & 8) == 8 --> (X & 8) >> 3
50545050
// Perform the xform if C1 is a single bit.
50555051
unsigned ShCt = C1.logBase2();
50565052
if (C1.isPowerOf2() &&
50575053
!TLI.shouldAvoidTransformToShift(ShValTy, ShCt)) {
5058-
return DAG.getNode(ISD::TRUNCATE, dl, VT,
5059-
DAG.getNode(ISD::SRL, dl, ShValTy, N0,
5060-
DAG.getConstant(ShCt, dl, ShiftTy)));
5054+
return DAG.getNode(
5055+
ISD::TRUNCATE, dl, VT,
5056+
DAG.getNode(ISD::SRL, dl, ShValTy, N0,
5057+
DAG.getShiftAmountConstant(
5058+
ShCt, ShValTy, dl, !DCI.isBeforeLegalize())));
50615059
}
50625060
}
50635061
}
50645062
}
50655063

50665064
if (C1.getSignificantBits() <= 64 &&
50675065
!isLegalICmpImmediate(C1.getSExtValue())) {
5068-
EVT ShiftTy = getShiftAmountTy(ShValTy, Layout, !DCI.isBeforeLegalize());
50695066
// (X & -256) == 256 -> (X >> 8) == 1
50705067
if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
50715068
N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
@@ -5074,9 +5071,10 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
50745071
if (AndRHSC.isNegatedPowerOf2() && (AndRHSC & C1) == C1) {
50755072
unsigned ShiftBits = AndRHSC.countr_zero();
50765073
if (!TLI.shouldAvoidTransformToShift(ShValTy, ShiftBits)) {
5077-
SDValue Shift =
5078-
DAG.getNode(ISD::SRL, dl, ShValTy, N0.getOperand(0),
5079-
DAG.getConstant(ShiftBits, dl, ShiftTy));
5074+
SDValue Shift = DAG.getNode(
5075+
ISD::SRL, dl, ShValTy, N0.getOperand(0),
5076+
DAG.getShiftAmountConstant(ShiftBits, ShValTy, dl,
5077+
!DCI.isBeforeLegalize()));
50805078
SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), dl, ShValTy);
50815079
return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
50825080
}
@@ -5103,8 +5101,10 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
51035101
if (ShiftBits && NewC.getSignificantBits() <= 64 &&
51045102
isLegalICmpImmediate(NewC.getSExtValue()) &&
51055103
!TLI.shouldAvoidTransformToShift(ShValTy, ShiftBits)) {
5106-
SDValue Shift = DAG.getNode(ISD::SRL, dl, ShValTy, N0,
5107-
DAG.getConstant(ShiftBits, dl, ShiftTy));
5104+
SDValue Shift =
5105+
DAG.getNode(ISD::SRL, dl, ShValTy, N0,
5106+
DAG.getShiftAmountConstant(ShiftBits, ShValTy, dl,
5107+
!DCI.isBeforeLegalize()));
51085108
SDValue CmpRHS = DAG.getConstant(NewC, dl, ShValTy);
51095109
return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond);
51105110
}
@@ -8944,7 +8944,6 @@ SDValue TargetLowering::expandABS(SDNode *N, SelectionDAG &DAG,
89448944
bool IsNegative) const {
89458945
SDLoc dl(N);
89468946
EVT VT = N->getValueType(0);
8947-
EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout());
89488947
SDValue Op = N->getOperand(0);
89498948

89508949
// abs(x) -> smax(x,sub(0,x))
@@ -8982,9 +8981,9 @@ SDValue TargetLowering::expandABS(SDNode *N, SelectionDAG &DAG,
89828981
return SDValue();
89838982

89848983
Op = DAG.getFreeze(Op);
8985-
SDValue Shift =
8986-
DAG.getNode(ISD::SRA, dl, VT, Op,
8987-
DAG.getConstant(VT.getScalarSizeInBits() - 1, dl, ShVT));
8984+
SDValue Shift = DAG.getNode(
8985+
ISD::SRA, dl, VT, Op,
8986+
DAG.getShiftAmountConstant(VT.getScalarSizeInBits() - 1, VT, dl));
89888987
SDValue Xor = DAG.getNode(ISD::XOR, dl, VT, Op, Shift);
89898988

89908989
// abs(x) -> Y = sra (X, size(X)-1); sub (xor (X, Y), Y)
@@ -9592,9 +9591,7 @@ TargetLowering::expandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG) const {
95929591
}
95939592

95949593
// aggregate the two parts
9595-
SDValue ShiftAmount =
9596-
DAG.getConstant(NumBits, dl, getShiftAmountTy(Hi.getValueType(),
9597-
DAG.getDataLayout()));
9594+
SDValue ShiftAmount = DAG.getShiftAmountConstant(NumBits, VT, dl);
95989595
SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
95999596
Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
96009597

@@ -9706,8 +9703,8 @@ SDValue TargetLowering::expandUnalignedStore(StoreSDNode *ST,
97069703
unsigned IncrementSize = NumBits / 8;
97079704

97089705
// Divide the stored value in two parts.
9709-
SDValue ShiftAmount = DAG.getConstant(
9710-
NumBits, dl, getShiftAmountTy(Val.getValueType(), DAG.getDataLayout()));
9706+
SDValue ShiftAmount =
9707+
DAG.getShiftAmountConstant(NumBits, Val.getValueType(), dl);
97119708
SDValue Lo = Val;
97129709
// If Val is a constant, replace the upper bits with 0. The SRL will constant
97139710
// fold and not use the upper bits. A smaller constant may be easier to
@@ -10351,9 +10348,8 @@ TargetLowering::expandFixedPointMul(SDNode *Node, SelectionDAG &DAG) const {
1035110348
// The result will need to be shifted right by the scale since both operands
1035210349
// are scaled. The result is given to us in 2 halves, so we only want part of
1035310350
// both in the result.
10354-
EVT ShiftTy = getShiftAmountTy(VT, DAG.getDataLayout());
1035510351
SDValue Result = DAG.getNode(ISD::FSHR, dl, VT, Hi, Lo,
10356-
DAG.getConstant(Scale, dl, ShiftTy));
10352+
DAG.getShiftAmountConstant(Scale, VT, dl));
1035710353
if (!Saturating)
1035810354
return Result;
1035910355

@@ -10381,7 +10377,7 @@ TargetLowering::expandFixedPointMul(SDNode *Node, SelectionDAG &DAG) const {
1038110377

1038210378
if (Scale == 0) {
1038310379
SDValue Sign = DAG.getNode(ISD::SRA, dl, VT, Lo,
10384-
DAG.getConstant(VTSize - 1, dl, ShiftTy));
10380+
DAG.getShiftAmountConstant(VTSize - 1, VT, dl));
1038510381
SDValue Overflow = DAG.getSetCC(dl, BoolVT, Hi, Sign, ISD::SETNE);
1038610382
// Saturated to SatMin if wide product is negative, and SatMax if wide
1038710383
// product is positive ...
@@ -10448,13 +10444,12 @@ TargetLowering::expandFixedPointDiv(unsigned Opcode, const SDLoc &dl,
1044810444
// RHS down by RHSShift, we can emit a regular division with a final scaling
1044910445
// factor of Scale.
1045010446

10451-
EVT ShiftTy = getShiftAmountTy(VT, DAG.getDataLayout());
1045210447
if (LHSShift)
1045310448
LHS = DAG.getNode(ISD::SHL, dl, VT, LHS,
10454-
DAG.getConstant(LHSShift, dl, ShiftTy));
10449+
DAG.getShiftAmountConstant(LHSShift, VT, dl));
1045510450
if (RHSShift)
1045610451
RHS = DAG.getNode(Signed ? ISD::SRA : ISD::SRL, dl, VT, RHS,
10457-
DAG.getConstant(RHSShift, dl, ShiftTy));
10452+
DAG.getShiftAmountConstant(RHSShift, VT, dl));
1045810453

1045910454
SDValue Quot;
1046010455
if (Signed) {
@@ -10597,8 +10592,7 @@ bool TargetLowering::expandMULO(SDNode *Node, SDValue &Result,
1059710592
if (C.isPowerOf2()) {
1059810593
// smulo(x, signed_min) is same as umulo(x, signed_min).
1059910594
bool UseArithShift = isSigned && !C.isMinSignedValue();
10600-
EVT ShiftAmtTy = getShiftAmountTy(VT, DAG.getDataLayout());
10601-
SDValue ShiftAmt = DAG.getConstant(C.logBase2(), dl, ShiftAmtTy);
10595+
SDValue ShiftAmt = DAG.getShiftAmountConstant(C.logBase2(), VT, dl);
1060210596
Result = DAG.getNode(ISD::SHL, dl, VT, LHS, ShiftAmt);
1060310597
Overflow = DAG.getSetCC(dl, SetCCVT,
1060410598
DAG.getNode(UseArithShift ? ISD::SRA : ISD::SRL,
@@ -10630,8 +10624,8 @@ bool TargetLowering::expandMULO(SDNode *Node, SDValue &Result,
1063010624
RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
1063110625
SDValue Mul = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
1063210626
BottomHalf = DAG.getNode(ISD::TRUNCATE, dl, VT, Mul);
10633-
SDValue ShiftAmt = DAG.getConstant(VT.getScalarSizeInBits(), dl,
10634-
getShiftAmountTy(WideVT, DAG.getDataLayout()));
10627+
SDValue ShiftAmt =
10628+
DAG.getShiftAmountConstant(VT.getScalarSizeInBits(), WideVT, dl);
1063510629
TopHalf = DAG.getNode(ISD::TRUNCATE, dl, VT,
1063610630
DAG.getNode(ISD::SRL, dl, WideVT, Mul, ShiftAmt));
1063710631
} else {
@@ -10643,9 +10637,8 @@ bool TargetLowering::expandMULO(SDNode *Node, SDValue &Result,
1064310637

1064410638
Result = BottomHalf;
1064510639
if (isSigned) {
10646-
SDValue ShiftAmt = DAG.getConstant(
10647-
VT.getScalarSizeInBits() - 1, dl,
10648-
getShiftAmountTy(BottomHalf.getValueType(), DAG.getDataLayout()));
10640+
SDValue ShiftAmt = DAG.getShiftAmountConstant(
10641+
VT.getScalarSizeInBits() - 1, BottomHalf.getValueType(), dl);
1064910642
SDValue Sign = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt);
1065010643
Overflow = DAG.getSetCC(dl, SetCCVT, TopHalf, Sign, ISD::SETNE);
1065110644
} else {

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