Code refactoring and test fixup.

Author: cdevadas

llvm/include/llvm/CodeGen/MachineBasicBlock.h

@@ -846,9 +846,8 @@ class MachineBasicBlock
 
   /// Return the first instruction in MBB after I that is not a PHI, label or
   /// debug.  This is the correct point to insert copies at the beginning of a
-  /// basic block. \p Reg is an optional argument passed during register
-  /// allocator to have additional target specific checks for its spill/copy
-  /// insertion.
+  /// basic block. \p Reg is the register being defined for a spill/split during
+  /// register allocation.
   iterator SkipPHIsLabelsAndDebug(iterator I, Register Reg = Register(),
                                   bool SkipPseudoOp = true);
 

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

@@ -8482,12 +8482,13 @@ bool SIInstrInfo::isBasicBlockPrologue(const MachineInstr &MI,
   // needed by the prolog. However, the insertions for scalar registers can
   // always be placed at the BB top as they are independent of the exec mask
   // value.
-  uint16_t Opc = MI.getOpcode();
-  const MachineFunction *MF = MI.getParent()->getParent();
-  const MachineRegisterInfo &MRI = MF->getRegInfo();
-  bool IsNullOrVectorRegister =
-      !Reg || !RI.isSGPRClass(RI.getRegClassForReg(MRI, Reg));
+  bool IsNullOrVectorRegister = true;
+  if (Reg) {
+    const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
+    IsNullOrVectorRegister = !RI.isSGPRClass(RI.getRegClassForReg(MRI, Reg));
+  }
 
+  uint16_t Opc = MI.getOpcode();
   // FIXME: Copies inserted in the block prolog for live-range split should also
   // be included.
   return IsNullOrVectorRegister &&