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[CodeGen][LoongArch] Set SINT_TO_FP/UINT_TO_FP to legal for vector types (#78924)
Support the following conversions: v4i32->v4f32, v2i64->v2f64(LSX) v8i32->v8f32, v4i64->v4f64(LASX) v4i32->v4f64, v4i64->v4f32(LASX)
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‎llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

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@@ -265,6 +265,8 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
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{ISD::SETNE, ISD::SETGE, ISD::SETGT, ISD::SETUGE, ISD::SETUGT}, VT,
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Expand);
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}
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setOperationAction({ISD::SINT_TO_FP, ISD::UINT_TO_FP},
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{MVT::v4i32, MVT::v2i64}, Legal);
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for (MVT VT : {MVT::v4f32, MVT::v2f64}) {
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setOperationAction({ISD::FADD, ISD::FSUB}, VT, Legal);
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setOperationAction({ISD::FMUL, ISD::FDIV}, VT, Legal);
@@ -307,6 +309,8 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
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{ISD::SETNE, ISD::SETGE, ISD::SETGT, ISD::SETUGE, ISD::SETUGT}, VT,
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Expand);
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}
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setOperationAction({ISD::SINT_TO_FP, ISD::UINT_TO_FP},
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{MVT::v8i32, MVT::v4i32, MVT::v4i64}, Legal);
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for (MVT VT : {MVT::v8f32, MVT::v4f64}) {
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setOperationAction({ISD::FADD, ISD::FSUB}, VT, Legal);
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setOperationAction({ISD::FMUL, ISD::FDIV}, VT, Legal);

‎llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1615,6 +1615,28 @@ foreach vt = [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64] in
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def : Pat<(fneg (v8f32 LASX256:$xj)), (XVBITREVI_W LASX256:$xj, 31)>;
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def : Pat<(fneg (v4f64 LASX256:$xj)), (XVBITREVI_D LASX256:$xj, 63)>;
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// XVFFINT_{S_W/D_L}
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def : Pat<(v8f32 (sint_to_fp v8i32:$vj)), (XVFFINT_S_W v8i32:$vj)>;
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def : Pat<(v4f64 (sint_to_fp v4i64:$vj)), (XVFFINT_D_L v4i64:$vj)>;
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def : Pat<(v4f64 (sint_to_fp v4i32:$vj)),
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(XVFFINT_D_L (VEXT2XV_D_W (SUBREG_TO_REG (i64 0), v4i32:$vj,
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sub_128)))>;
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def : Pat<(v4f32 (sint_to_fp v4i64:$vj)),
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(EXTRACT_SUBREG (XVFCVT_S_D (XVPERMI_D (XVFFINT_D_L v4i64:$vj), 238),
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(XVFFINT_D_L v4i64:$vj)),
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sub_128)>;
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// XVFFINT_{S_WU/D_LU}
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def : Pat<(v8f32 (uint_to_fp v8i32:$vj)), (XVFFINT_S_WU v8i32:$vj)>;
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def : Pat<(v4f64 (uint_to_fp v4i64:$vj)), (XVFFINT_D_LU v4i64:$vj)>;
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def : Pat<(v4f64 (uint_to_fp v4i32:$vj)),
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(XVFFINT_D_LU (VEXT2XV_DU_WU (SUBREG_TO_REG (i64 0), v4i32:$vj,
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sub_128)))>;
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def : Pat<(v4f32 (uint_to_fp v4i64:$vj)),
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(EXTRACT_SUBREG (XVFCVT_S_D (XVPERMI_D (XVFFINT_D_LU v4i64:$vj), 238),
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(XVFFINT_D_LU v4i64:$vj)),
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sub_128)>;
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} // Predicates = [HasExtLASX]
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/// Intrinsic pattern

‎llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td

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@@ -1746,6 +1746,14 @@ foreach vt = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in
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def : Pat<(fneg (v4f32 LSX128:$vj)), (VBITREVI_W LSX128:$vj, 31)>;
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def : Pat<(fneg (v2f64 LSX128:$vj)), (VBITREVI_D LSX128:$vj, 63)>;
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// VFFINT_{S_W/D_L}
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def : Pat<(v4f32 (sint_to_fp v4i32:$vj)), (VFFINT_S_W v4i32:$vj)>;
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def : Pat<(v2f64 (sint_to_fp v2i64:$vj)), (VFFINT_D_L v2i64:$vj)>;
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// VFFINT_{S_WU/D_LU}
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def : Pat<(v4f32 (uint_to_fp v4i32:$vj)), (VFFINT_S_WU v4i32:$vj)>;
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def : Pat<(v2f64 (uint_to_fp v2i64:$vj)), (VFFINT_D_LU v2i64:$vj)>;
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} // Predicates = [HasExtLSX]
17501758

17511759
/// Intrinsic pattern

‎llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sitofp.ll

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@@ -0,0 +1,57 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
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; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
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define void @sitofp_v8i32_v8f32(ptr %res, ptr %in){
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; CHECK-LABEL: sitofp_v8i32_v8f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvld $xr0, $a1, 0
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; CHECK-NEXT: xvffint.s.w $xr0, $xr0
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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%v0 = load <8 x i32>, ptr %in
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%v1 = sitofp <8 x i32> %v0 to <8 x float>
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store <8 x float> %v1, ptr %res
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ret void
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}
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define void @sitofp_v4f64_v4f64(ptr %res, ptr %in){
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; CHECK-LABEL: sitofp_v4f64_v4f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvld $xr0, $a1, 0
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; CHECK-NEXT: xvffint.d.l $xr0, $xr0
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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%v0 = load <4 x i64>, ptr %in
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%v1 = sitofp <4 x i64> %v0 to <4 x double>
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store <4 x double> %v1, ptr %res
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ret void
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}
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define void @sitofp_v4i64_v4f32(ptr %res, ptr %in){
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; CHECK-LABEL: sitofp_v4i64_v4f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvld $xr0, $a1, 0
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; CHECK-NEXT: xvffint.d.l $xr0, $xr0
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 238
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; CHECK-NEXT: xvfcvt.s.d $xr0, $xr1, $xr0
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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%v0 = load <4 x i64>, ptr %in
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%v1 = sitofp <4 x i64> %v0 to <4 x float>
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store <4 x float> %v1, ptr %res
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ret void
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}
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define void @sitofp_v4i32_v4f64(ptr %res, ptr %in){
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; CHECK-LABEL: sitofp_v4i32_v4f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vext2xv.d.w $xr0, $xr0
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; CHECK-NEXT: xvffint.d.l $xr0, $xr0
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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%v0 = load <4 x i32>, ptr %in
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%v1 = sitofp <4 x i32> %v0 to <4 x double>
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store <4 x double> %v1, ptr %res
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ret void
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}

‎llvm/test/CodeGen/LoongArch/lasx/ir-instruction/uitofp.ll

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@@ -0,0 +1,57 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
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; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
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define void @uitofp_v8i32_v8f32(ptr %res, ptr %in){
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; CHECK-LABEL: uitofp_v8i32_v8f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvld $xr0, $a1, 0
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; CHECK-NEXT: xvffint.s.wu $xr0, $xr0
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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%v0 = load <8 x i32>, ptr %in
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%v1 = uitofp <8 x i32> %v0 to <8 x float>
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store <8 x float> %v1, ptr %res
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ret void
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}
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define void @uitofp_v4f64_v4f64(ptr %res, ptr %in){
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; CHECK-LABEL: uitofp_v4f64_v4f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvld $xr0, $a1, 0
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; CHECK-NEXT: xvffint.d.lu $xr0, $xr0
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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%v0 = load <4 x i64>, ptr %in
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%v1 = uitofp <4 x i64> %v0 to <4 x double>
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store <4 x double> %v1, ptr %res
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ret void
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}
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define void @uitofp_v4i64_v4f32(ptr %res, ptr %in){
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; CHECK-LABEL: uitofp_v4i64_v4f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvld $xr0, $a1, 0
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; CHECK-NEXT: xvffint.d.lu $xr0, $xr0
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 238
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; CHECK-NEXT: xvfcvt.s.d $xr0, $xr1, $xr0
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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%v0 = load <4 x i64>, ptr %in
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%v1 = uitofp <4 x i64> %v0 to <4 x float>
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store <4 x float> %v1, ptr %res
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ret void
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}
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define void @uitofp_v4i32_v4f64(ptr %res, ptr %in){
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; CHECK-LABEL: uitofp_v4i32_v4f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vext2xv.du.wu $xr0, $xr0
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; CHECK-NEXT: xvffint.d.lu $xr0, $xr0
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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%v0 = load <4 x i32>, ptr %in
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%v1 = uitofp <4 x i32> %v0 to <4 x double>
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store <4 x double> %v1, ptr %res
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ret void
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}

‎llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sitofp.ll

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@@ -0,0 +1,28 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
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; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
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define void @sitofp_v4i32_v4f32(ptr %res, ptr %in){
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; CHECK-LABEL: sitofp_v4i32_v4f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vffint.s.w $vr0, $vr0
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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%v0 = load <4 x i32>, ptr %in
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%v1 = sitofp <4 x i32> %v0 to <4 x float>
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store <4 x float> %v1, ptr %res
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ret void
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}
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define void @sitofp_v2i64_v2f64(ptr %res, ptr %in){
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; CHECK-LABEL: sitofp_v2i64_v2f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vffint.d.l $vr0, $vr0
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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%v0 = load <2 x i64>, ptr %in
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%v1 = sitofp <2 x i64> %v0 to <2 x double>
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store <2 x double> %v1, ptr %res
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ret void
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}

‎llvm/test/CodeGen/LoongArch/lsx/ir-instruction/uitofp.ll

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@@ -0,0 +1,28 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
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; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
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4+
define void @uitofp_v4i32_v4f32(ptr %res, ptr %in){
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; CHECK-LABEL: uitofp_v4i32_v4f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vffint.s.wu $vr0, $vr0
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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%v0 = load <4 x i32>, ptr %in
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%v1 = uitofp <4 x i32> %v0 to <4 x float>
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store <4 x float> %v1, ptr %res
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ret void
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}
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define void @uitofp_v2i64_v2f64(ptr %res, ptr %in){
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; CHECK-LABEL: uitofp_v2i64_v2f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vffint.d.lu $vr0, $vr0
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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%v0 = load <2 x i64>, ptr %in
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%v1 = uitofp <2 x i64> %v0 to <2 x double>
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store <2 x double> %v1, ptr %res
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ret void
28+
}

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