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[RISCV] Implement isElementTypeLegalForScalableVector TTI hook
This brings us into alignment with AArch64, and in the process fixes a compiler crash bug in uniform store handling in the vectorizer. Before the recent invalid cost bailout work, this would have also avoided crashes on invalid costs in some cases. I honestly think the vectorizer should gracefully bailout on uniform stores it can't use a scatter for, but it doesn't, so lets take the path of least resistance here. It's also possible that there are other vectorizer bugs AArch64 isn't seeing because of this hook; we don't want to be finding them either. Differential Revision: https://reviews.llvm.org/D127514
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‎llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h

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@@ -105,6 +105,10 @@ class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
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Optional<FastMathFlags> FMF,
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TTI::TargetCostKind CostKind);
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bool isElementTypeLegalForScalableVector(Type *Ty) const {
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return TLI->isLegalElementTypeForRVV(Ty);
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}
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bool isLegalMaskedLoadStore(Type *DataType, Align Alignment) {
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if (!ST->hasVInstructions())
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return false;

‎llvm/test/Transforms/LoopVectorize/RISCV/illegal-type.ll

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -loop-vectorize -mattr=+v -force-vector-width=4 -scalable-vectorization=on -S 2>&1 | FileCheck %s
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target triple = "riscv64-linux-gnu"
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;
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define dso_local void @loop_i128(i128* nocapture %ptr, i64 %N) {
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; CHECK-LABEL: @loop_i128(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[FOR_BODY:%.*]]
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; CHECK: for.body:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[FOR_BODY]] ]
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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i128, i128* [[PTR:%.*]], i64 [[IV]]
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; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[ARRAYIDX]], align 16
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; CHECK-NEXT: [[ADD:%.*]] = add nsw i128 [[TMP0]], 42
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; CHECK-NEXT: store i128 [[ADD]], i128* [[ARRAYIDX]], align 16
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; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
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; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N:%.*]]
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; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_END:%.*]], label [[FOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: for.end:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %for.body
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for.body:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
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%arrayidx = getelementptr inbounds i128, i128* %ptr, i64 %iv
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%0 = load i128, i128* %arrayidx, align 16
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%add = add nsw i128 %0, 42
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store i128 %add, i128* %arrayidx, align 16
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%iv.next = add i64 %iv, 1
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%exitcond.not = icmp eq i64 %iv.next, %N
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br i1 %exitcond.not, label %for.end, label %for.body, !llvm.loop !0
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for.end:
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ret void
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}
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define dso_local void @loop_f128(fp128* nocapture %ptr, i64 %N) {
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; CHECK-LABEL: @loop_f128(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[FOR_BODY:%.*]]
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; CHECK: for.body:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[FOR_BODY]] ]
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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds fp128, fp128* [[PTR:%.*]], i64 [[IV]]
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; CHECK-NEXT: [[TMP0:%.*]] = load fp128, fp128* [[ARRAYIDX]], align 16
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; CHECK-NEXT: [[ADD:%.*]] = fsub fp128 [[TMP0]], 0xL00000000000000008000000000000000
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; CHECK-NEXT: store fp128 [[ADD]], fp128* [[ARRAYIDX]], align 16
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
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; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N:%.*]]
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; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_END:%.*]], label [[FOR_BODY]], !llvm.loop [[LOOP0]]
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; CHECK: for.end:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %for.body
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for.body:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
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%arrayidx = getelementptr inbounds fp128, fp128* %ptr, i64 %iv
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%0 = load fp128, fp128* %arrayidx, align 16
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%add = fsub fp128 %0, 0xL00000000000000008000000000000000
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store fp128 %add, fp128* %arrayidx, align 16
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%iv.next = add nuw nsw i64 %iv, 1
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%exitcond.not = icmp eq i64 %iv.next, %N
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br i1 %exitcond.not, label %for.end, label %for.body, !llvm.loop !0
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for.end:
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ret void
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}
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define dso_local void @loop_invariant_i128(i128* nocapture %ptr, i128 %val, i64 %N) {
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; CHECK-LABEL: @loop_invariant_i128(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[FOR_BODY:%.*]]
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; CHECK: for.body:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[FOR_BODY]] ]
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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i128, i128* [[PTR:%.*]], i64 [[IV]]
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; CHECK-NEXT: store i128 [[VAL:%.*]], i128* [[ARRAYIDX]], align 16
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
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; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N:%.*]]
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; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_END:%.*]], label [[FOR_BODY]], !llvm.loop [[LOOP0]]
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; CHECK: for.end:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %for.body
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for.body:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
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%arrayidx = getelementptr inbounds i128, i128* %ptr, i64 %iv
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store i128 %val, i128* %arrayidx, align 16
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%iv.next = add nuw nsw i64 %iv, 1
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%exitcond.not = icmp eq i64 %iv.next, %N
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br i1 %exitcond.not, label %for.end, label %for.body, !llvm.loop !0
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for.end:
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ret void
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}
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define void @uniform_store_i1(i1* noalias %dst, i64* noalias %start, i64 %N) {
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; CHECK-LABEL: @uniform_store_i1(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[FOR_BODY:%.*]]
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; CHECK: for.body:
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; CHECK-NEXT: [[FIRST_SROA:%.*]] = phi i64* [ [[INCDEC_PTR:%.*]], [[FOR_BODY]] ], [ [[START:%.*]], [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY]] ]
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; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
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; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[FIRST_SROA]], align 4
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; CHECK-NEXT: [[INCDEC_PTR]] = getelementptr inbounds i64, i64* [[FIRST_SROA]], i64 1
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; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i64* [[INCDEC_PTR]], [[START]]
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; CHECK-NEXT: store i1 [[CMP_NOT]], i1* [[DST:%.*]], align 1
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; CHECK-NEXT: [[CMP:%.*]] = icmp ult i64 [[IV]], [[N:%.*]]
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; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[END:%.*]], !llvm.loop [[LOOP0]]
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; CHECK: end:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %for.body
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for.body:
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%first.sroa = phi i64* [ %incdec.ptr, %for.body ], [ %start, %entry ]
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%iv = phi i64 [ %iv.next, %for.body ], [ 0, %entry ]
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%iv.next = add i64 %iv, 1
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%0 = load i64, i64* %first.sroa
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%incdec.ptr = getelementptr inbounds i64, i64* %first.sroa, i64 1
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%cmp.not = icmp eq i64* %incdec.ptr, %start
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store i1 %cmp.not, i1* %dst
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%cmp = icmp ult i64 %iv, %N
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br i1 %cmp, label %for.body, label %end, !llvm.loop !0
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end:
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ret void
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}
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define dso_local void @loop_fixed_width_i128(i128* nocapture %ptr, i64 %N) {
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; CHECK-LABEL: @loop_fixed_width_i128(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[FOR_BODY:%.*]]
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; CHECK: for.body:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[FOR_BODY]] ]
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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i128, i128* [[PTR:%.*]], i64 [[IV]]
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; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[ARRAYIDX]], align 16
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; CHECK-NEXT: [[ADD:%.*]] = add nsw i128 [[TMP0]], 42
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; CHECK-NEXT: store i128 [[ADD]], i128* [[ARRAYIDX]], align 16
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; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
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; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N:%.*]]
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; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_END:%.*]], label [[FOR_BODY]]
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; CHECK: for.end:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %for.body
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for.body:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
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%arrayidx = getelementptr inbounds i128, i128* %ptr, i64 %iv
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%0 = load i128, i128* %arrayidx, align 16
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%add = add nsw i128 %0, 42
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store i128 %add, i128* %arrayidx, align 16
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%iv.next = add i64 %iv, 1
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%exitcond.not = icmp eq i64 %iv.next, %N
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br i1 %exitcond.not, label %for.end, label %for.body
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for.end:
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ret void
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}
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!0 = distinct !{!0, !1}
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!1 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}

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