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Revert "[libclc] Refactor build system to allow in-tree builds (#87622)"
This reverts commit 9029e6e, which was committed by mistake with the wrong message and fails https://lab.llvm.org/buildbot/#/builders/221/builds/21958.
1 parent d7be9d2 commit f7cc224

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-50
lines changed

2 files changed

+15
-50
lines changed

llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp

Lines changed: 3 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -305,32 +305,7 @@ static bool isCommutative(Instruction *I) {
305305
if (auto *Cmp = dyn_cast<CmpInst>(I))
306306
return Cmp->isCommutative();
307307
if (auto *BO = dyn_cast<BinaryOperator>(I))
308-
return BO->isCommutative() ||
309-
(BO->getOpcode() == Instruction::Sub &&
310-
!BO->hasNUsesOrMore(UsesLimit) &&
311-
all_of(
312-
BO->uses(),
313-
[](const Use &U) {
314-
// Commutative, if icmp eq/ne sub, 0
315-
ICmpInst::Predicate Pred;
316-
if (match(U.getUser(),
317-
m_ICmp(Pred, m_Specific(U.get()), m_Zero())) &&
318-
(Pred == ICmpInst::ICMP_EQ || Pred == ICmpInst::ICMP_NE))
319-
return true;
320-
// Commutative, if abs(sub nsw, true) or abs(sub, false).
321-
ConstantInt *Flag;
322-
return match(U.getUser(),
323-
m_Intrinsic<Intrinsic::abs>(
324-
m_Specific(U.get()), m_ConstantInt(Flag))) &&
325-
(!cast<Instruction>(U.get())->hasNoSignedWrap() ||
326-
Flag->isOne());
327-
})) ||
328-
(BO->getOpcode() == Instruction::FSub &&
329-
!BO->hasNUsesOrMore(UsesLimit) &&
330-
all_of(BO->uses(), [](const Use &U) {
331-
return match(U.getUser(),
332-
m_Intrinsic<Intrinsic::fabs>(m_Specific(U.get())));
333-
}));
308+
return BO->isCommutative();
334309
return I->isCommutative();
335310
}
336311

@@ -6863,7 +6838,7 @@ void BoUpSLP::buildTree_rec(ArrayRef<Value *> VL, unsigned Depth,
68636838

68646839
// Sort operands of the instructions so that each side is more likely to
68656840
// have the same opcode.
6866-
if (isa<BinaryOperator>(VL0) && isCommutative(VL0)) {
6841+
if (isa<BinaryOperator>(VL0) && VL0->isCommutative()) {
68676842
ValueList Left, Right;
68686843
reorderInputsAccordingToOpcode(VL, Left, Right, *this);
68696844
TE->setOperand(0, Left);
@@ -12591,15 +12566,8 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E, bool PostponedPHIs) {
1259112566
static_cast<Instruction::BinaryOps>(E->getOpcode()), LHS,
1259212567
RHS);
1259312568
propagateIRFlags(V, E->Scalars, VL0, It == MinBWs.end());
12594-
if (auto *I = dyn_cast<Instruction>(V)) {
12569+
if (auto *I = dyn_cast<Instruction>(V))
1259512570
V = propagateMetadata(I, E->Scalars);
12596-
// Drop nuw flags for abs(sub(commutative), true).
12597-
if (!MinBWs.contains(E) && ShuffleOrOp == Instruction::Sub &&
12598-
any_of(E->Scalars, [](Value *V) {
12599-
return isCommutative(cast<Instruction>(V));
12600-
}))
12601-
I->setHasNoUnsignedWrap(/*b=*/false);
12602-
}
1260312571

1260412572
V = FinalShuffle(V, E, VecTy);
1260512573

@@ -12925,19 +12893,6 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E, bool PostponedPHIs) {
1292512893

1292612894
propagateIRFlags(V0, OpScalars, E->getMainOp(), It == MinBWs.end());
1292712895
propagateIRFlags(V1, AltScalars, E->getAltOp(), It == MinBWs.end());
12928-
auto DropNuwFlag = [&](Value *Vec, unsigned Opcode) {
12929-
// Drop nuw flags for abs(sub(commutative), true).
12930-
if (auto *I = dyn_cast<Instruction>(Vec);
12931-
I && Opcode == Instruction::Sub && !MinBWs.contains(E) &&
12932-
any_of(E->Scalars, [](Value *V) {
12933-
auto *I = cast<Instruction>(V);
12934-
return I->getOpcode() == Instruction::Sub &&
12935-
isCommutative(cast<Instruction>(V));
12936-
}))
12937-
I->setHasNoUnsignedWrap(/*b=*/false);
12938-
};
12939-
DropNuwFlag(V0, E->getOpcode());
12940-
DropNuwFlag(V1, E->getAltOpcode());
1294112896

1294212897
Value *V = Builder.CreateShuffleVector(V0, V1, Mask);
1294312898
if (auto *I = dyn_cast<Instruction>(V)) {

llvm/test/Transforms/SLPVectorizer/X86/store-abs-minbitwidth.ll

Lines changed: 12 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,9 +4,19 @@
44

55
define i32 @test(ptr noalias %in, ptr noalias %inn, ptr %out) {
66
; CHECK-LABEL: @test(
7-
; CHECK-NEXT: [[TMP7:%.*]] = load <4 x i8>, ptr [[IN:%.*]], align 1
8-
; CHECK-NEXT: [[TMP11:%.*]] = load <4 x i8>, ptr [[INN:%.*]], align 1
7+
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i8>, ptr [[IN:%.*]], align 1
8+
; CHECK-NEXT: [[GEP_2:%.*]] = getelementptr inbounds i8, ptr [[IN]], i64 2
9+
; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i8>, ptr [[GEP_2]], align 1
10+
; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i8>, ptr [[INN:%.*]], align 1
11+
; CHECK-NEXT: [[GEP_5:%.*]] = getelementptr inbounds i8, ptr [[INN]], i64 2
12+
; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i8>, ptr [[GEP_5]], align 1
13+
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x i8> [[TMP3]], <2 x i8> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
14+
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x i8> [[TMP2]], <2 x i8> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
15+
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i8> [[TMP5]], <4 x i8> [[TMP6]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
916
; CHECK-NEXT: [[TMP8:%.*]] = sext <4 x i8> [[TMP7]] to <4 x i16>
17+
; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <2 x i8> [[TMP1]], <2 x i8> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
18+
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <2 x i8> [[TMP4]], <2 x i8> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
19+
; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <4 x i8> [[TMP9]], <4 x i8> [[TMP10]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
1020
; CHECK-NEXT: [[TMP12:%.*]] = sext <4 x i8> [[TMP11]] to <4 x i16>
1121
; CHECK-NEXT: [[TMP13:%.*]] = sub <4 x i16> [[TMP12]], [[TMP8]]
1222
; CHECK-NEXT: [[TMP15:%.*]] = call <4 x i16> @llvm.abs.v4i16(<4 x i16> [[TMP13]], i1 false)

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