Skip to content

Commit f83d09a

Browse files
AaronBallmanAaronBallman
authored
Revert "[RISCV] Remove B and Zbc extension from Andes series cpus." (#144402)
Reverts #144022 This has been failing postcommit CI for two days: https://lab.llvm.org/buildbot/#/builders/63
1 parent fcc10e5 commit f83d09a

File tree

8 files changed

+41
-7
lines changed

8 files changed

+41
-7
lines changed

‎clang/test/Driver/print-enabled-extensions/riscv-andes-a25.c

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,7 @@
1010
// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)
1111
// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point)
1212
// CHECK-NEXT: c 2.0 'C' (Compressed Instructions)
13+
// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
1314
// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
1415
// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
1516
// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication)
@@ -18,8 +19,12 @@
1819
// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores)
1920
// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions)
2021
// CHECK-NEXT: zcf 1.0 'Zcf' (Compressed Single-Precision Floating-Point Instructions)
22+
// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions)
23+
// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation)
24+
// CHECK-NEXT: zbc 1.0 'Zbc' (Carry-Less Multiplication)
25+
// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions)
2126
// CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension)
2227
// CHECK-EMPTY:
2328
// CHECK-NEXT: Experimental extensions
2429
// CHECK-EMPTY:
25-
// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_xandesperf5p0
30+
// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0_xandesperf5p0

‎clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,7 @@
1010
// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)
1111
// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point)
1212
// CHECK-NEXT: c 2.0 'C' (Compressed Instructions)
13+
// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
1314
// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
1415
// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
1516
// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication)
@@ -18,8 +19,11 @@
1819
// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores)
1920
// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions)
2021
// CHECK-NEXT: zcf 1.0 'Zcf' (Compressed Single-Precision Floating-Point Instructions)
22+
// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions)
23+
// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation)
24+
// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions)
2125
// CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension)
2226
// CHECK-EMPTY:
2327
// CHECK-NEXT: Experimental extensions
2428
// CHECK-EMPTY:
25-
// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_xandesperf5p0
29+
// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_zba1p0_zbb1p0_zbs1p0_xandesperf5p0

‎clang/test/Driver/print-enabled-extensions/riscv-andes-ax25.c

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,15 +10,20 @@
1010
// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)
1111
// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point)
1212
// CHECK-NEXT: c 2.0 'C' (Compressed Instructions)
13+
// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
1314
// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
1415
// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
1516
// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication)
1617
// CHECK-NEXT: zaamo 1.0 'Zaamo' (Atomic Memory Operations)
1718
// CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional)
1819
// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores)
1920
// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions)
21+
// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions)
22+
// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation)
23+
// CHECK-NEXT: zbc 1.0 'Zbc' (Carry-Less Multiplication)
24+
// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions)
2025
// CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension)
2126
// CHECK-EMPTY:
2227
// CHECK-NEXT: Experimental extensions
2328
// CHECK-EMPTY:
24-
// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_xandesperf5p0
29+
// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0_xandesperf5p0

‎clang/test/Driver/print-enabled-extensions/riscv-andes-ax45.c

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,15 +10,19 @@
1010
// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)
1111
// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point)
1212
// CHECK-NEXT: c 2.0 'C' (Compressed Instructions)
13+
// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
1314
// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
1415
// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
1516
// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication)
1617
// CHECK-NEXT: zaamo 1.0 'Zaamo' (Atomic Memory Operations)
1718
// CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional)
1819
// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores)
1920
// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions)
21+
// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions)
22+
// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation)
23+
// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions)
2024
// CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension)
2125
// CHECK-EMPTY:
2226
// CHECK-NEXT: Experimental extensions
2327
// CHECK-EMPTY:
24-
// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_xandesperf5p0
28+
// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0_zbs1p0_xandesperf5p0

‎clang/test/Driver/print-enabled-extensions/riscv-andes-n45.c

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,7 @@
1010
// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)
1111
// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point)
1212
// CHECK-NEXT: c 2.0 'C' (Compressed Instructions)
13+
// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
1314
// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
1415
// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
1516
// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication)
@@ -18,8 +19,11 @@
1819
// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores)
1920
// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions)
2021
// CHECK-NEXT: zcf 1.0 'Zcf' (Compressed Single-Precision Floating-Point Instructions)
22+
// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions)
23+
// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation)
24+
// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions)
2125
// CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension)
2226
// CHECK-EMPTY:
2327
// CHECK-NEXT: Experimental extensions
2428
// CHECK-EMPTY:
25-
// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_xandesperf5p0
29+
// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_zba1p0_zbb1p0_zbs1p0_xandesperf5p0

‎clang/test/Driver/print-enabled-extensions/riscv-andes-nx45.c

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,15 +10,19 @@
1010
// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)
1111
// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point)
1212
// CHECK-NEXT: c 2.0 'C' (Compressed Instructions)
13+
// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
1314
// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
1415
// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
1516
// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication)
1617
// CHECK-NEXT: zaamo 1.0 'Zaamo' (Atomic Memory Operations)
1718
// CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional)
1819
// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores)
1920
// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions)
21+
// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions)
22+
// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation)
23+
// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions)
2024
// CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension)
2125
// CHECK-EMPTY:
2226
// CHECK-NEXT: Experimental extensions
2327
// CHECK-EMPTY:
24-
// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_xandesperf5p0
28+
// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0_zbs1p0_xandesperf5p0

‎llvm/lib/Target/RISCV/RISCVProcessors.td

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -703,6 +703,8 @@ def ANDES_A25 : RISCVProcessorModel<"andes-a25",
703703
FeatureStdExtF,
704704
FeatureStdExtD,
705705
FeatureStdExtC,
706+
FeatureStdExtB,
707+
FeatureStdExtZbc,
706708
FeatureVendorXAndesPerf]>;
707709

708710
def ANDES_AX25 : RISCVProcessorModel<"andes-ax25",
@@ -716,6 +718,8 @@ def ANDES_AX25 : RISCVProcessorModel<"andes-ax25",
716718
FeatureStdExtF,
717719
FeatureStdExtD,
718720
FeatureStdExtC,
721+
FeatureStdExtB,
722+
FeatureStdExtZbc,
719723
FeatureVendorXAndesPerf]>;
720724

721725
defvar Andes45TuneFeatures = [TuneAndes45,
@@ -737,6 +741,7 @@ def ANDES_N45 : RISCVProcessorModel<"andes-n45",
737741
FeatureStdExtF,
738742
FeatureStdExtD,
739743
FeatureStdExtC,
744+
FeatureStdExtB,
740745
FeatureVendorXAndesPerf],
741746
Andes45TuneFeatures>;
742747

@@ -751,6 +756,7 @@ def ANDES_NX45 : RISCVProcessorModel<"andes-nx45",
751756
FeatureStdExtF,
752757
FeatureStdExtD,
753758
FeatureStdExtC,
759+
FeatureStdExtB,
754760
FeatureVendorXAndesPerf],
755761
Andes45TuneFeatures>;
756762

@@ -765,6 +771,7 @@ def ANDES_A45 : RISCVProcessorModel<"andes-a45",
765771
FeatureStdExtF,
766772
FeatureStdExtD,
767773
FeatureStdExtC,
774+
FeatureStdExtB,
768775
FeatureVendorXAndesPerf],
769776
Andes45TuneFeatures>;
770777

@@ -779,5 +786,6 @@ def ANDES_AX45 : RISCVProcessorModel<"andes-ax45",
779786
FeatureStdExtF,
780787
FeatureStdExtD,
781788
FeatureStdExtC,
789+
FeatureStdExtB,
782790
FeatureVendorXAndesPerf],
783791
Andes45TuneFeatures>;

‎llvm/test/tools/llvm-mca/RISCV/Andes45/gpr.s

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
2-
# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-nx45 -mattr=+b,+zbc -timeline -iterations=1 < %s | FileCheck %s
2+
# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-nx45 -mattr=+zbc -timeline -iterations=1 < %s | FileCheck %s
33

44
# Two ALUs without dependency can be dispatched in the same cycle.
55
add a0, a0, a0

0 commit comments

Comments
 (0)