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[AMDGPU] Make flat_offset a 32-bit operand instead of 16-bits
Differential Revision: https://reviews.llvm.org/D142549
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‎llvm/lib/Target/AMDGPU/FLATInstructions.td

Lines changed: 26 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -937,81 +937,81 @@ let OtherPredicates = [isGFX90APlus] in
937937

938938
// Patterns for global loads with no offset.
939939
class FlatLoadPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat <
940-
(vt (node (FlatOffset i64:$vaddr, i16:$offset))),
940+
(vt (node (FlatOffset i64:$vaddr, i32:$offset))),
941941
(inst $vaddr, $offset)
942942
>;
943943

944944
class FlatLoadPat_D16 <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat <
945-
(node (FlatOffset (i64 VReg_64:$vaddr), i16:$offset), vt:$in),
945+
(node (FlatOffset (i64 VReg_64:$vaddr), i32:$offset), vt:$in),
946946
(inst $vaddr, $offset, 0, $in)
947947
>;
948948

949949
class FlatSignedLoadPat_D16 <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat <
950-
(node (GlobalOffset (i64 VReg_64:$vaddr), i16:$offset), vt:$in),
950+
(node (GlobalOffset (i64 VReg_64:$vaddr), i32:$offset), vt:$in),
951951
(inst $vaddr, $offset, 0, $in)
952952
>;
953953

954954
class GlobalLoadSaddrPat_D16 <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat <
955-
(vt (node (GlobalSAddr (i64 SReg_64:$saddr), (i32 VGPR_32:$voffset), i16:$offset), vt:$in)),
955+
(vt (node (GlobalSAddr (i64 SReg_64:$saddr), (i32 VGPR_32:$voffset), i32:$offset), vt:$in)),
956956
(inst $saddr, $voffset, $offset, 0, $in)
957957
>;
958958

959959
class FlatLoadSignedPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat <
960-
(vt (node (GlobalOffset (i64 VReg_64:$vaddr), i16:$offset))),
960+
(vt (node (GlobalOffset (i64 VReg_64:$vaddr), i32:$offset))),
961961
(inst $vaddr, $offset)
962962
>;
963963

964964
class GlobalLoadSaddrPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat <
965-
(vt (node (GlobalSAddr (i64 SReg_64:$saddr), (i32 VGPR_32:$voffset), i16:$offset))),
965+
(vt (node (GlobalSAddr (i64 SReg_64:$saddr), (i32 VGPR_32:$voffset), i32:$offset))),
966966
(inst $saddr, $voffset, $offset, 0)
967967
>;
968968

969969
class GlobalStoreSaddrPat <FLAT_Pseudo inst, SDPatternOperator node,
970970
ValueType vt> : GCNPat <
971-
(node vt:$data, (GlobalSAddr (i64 SReg_64:$saddr), (i32 VGPR_32:$voffset), i16:$offset)),
971+
(node vt:$data, (GlobalSAddr (i64 SReg_64:$saddr), (i32 VGPR_32:$voffset), i32:$offset)),
972972
(inst $voffset, getVregSrcForVT<vt>.ret:$data, $saddr, $offset)
973973
>;
974974

975975
class GlobalAtomicStoreSaddrPat <FLAT_Pseudo inst, SDPatternOperator node,
976976
ValueType vt> : GCNPat <
977-
(node (GlobalSAddr (i64 SReg_64:$saddr), (i32 VGPR_32:$voffset), i16:$offset), vt:$data),
977+
(node (GlobalSAddr (i64 SReg_64:$saddr), (i32 VGPR_32:$voffset), i32:$offset), vt:$data),
978978
(inst $voffset, getVregSrcForVT<vt>.ret:$data, $saddr, $offset)
979979
>;
980980

981981
class GlobalAtomicSaddrPat <FLAT_Pseudo inst, SDPatternOperator node,
982982
ValueType vt, ValueType data_vt = vt> : GCNPat <
983-
(vt (node (GlobalSAddr (i64 SReg_64:$saddr), (i32 VGPR_32:$voffset), i16:$offset), data_vt:$data)),
983+
(vt (node (GlobalSAddr (i64 SReg_64:$saddr), (i32 VGPR_32:$voffset), i32:$offset), data_vt:$data)),
984984
(inst $voffset, getVregSrcForVT<data_vt>.ret:$data, $saddr, $offset)
985985
>;
986986

987987
class GlobalAtomicNoRtnSaddrPat <FLAT_Pseudo inst, SDPatternOperator node,
988988
ValueType vt> : GCNPat <
989-
(node (GlobalSAddr (i64 SReg_64:$saddr), (i32 VGPR_32:$voffset), i16:$offset), vt:$data),
989+
(node (GlobalSAddr (i64 SReg_64:$saddr), (i32 VGPR_32:$voffset), i32:$offset), vt:$data),
990990
(inst $voffset, getVregSrcForVT<vt>.ret:$data, $saddr, $offset)
991991
>;
992992

993993
class FlatStorePat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat <
994-
(node vt:$data, (FlatOffset i64:$vaddr, i16:$offset)),
994+
(node vt:$data, (FlatOffset i64:$vaddr, i32:$offset)),
995995
(inst $vaddr, getVregSrcForVT<vt>.ret:$data, $offset)
996996
>;
997997

998998
class FlatStoreSignedPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat <
999-
(node vt:$data, (GlobalOffset i64:$vaddr, i16:$offset)),
999+
(node vt:$data, (GlobalOffset i64:$vaddr, i32:$offset)),
10001000
(inst $vaddr, getVregSrcForVT<vt>.ret:$data, $offset)
10011001
>;
10021002

10031003
class FlatStoreAtomicPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat <
10041004
// atomic store follows atomic binop convention so the address comes
10051005
// first.
1006-
(node (FlatOffset i64:$vaddr, i16:$offset), vt:$data),
1006+
(node (FlatOffset i64:$vaddr, i32:$offset), vt:$data),
10071007
(inst $vaddr, getVregSrcForVT<vt>.ret:$data, $offset)
10081008
>;
10091009

10101010
class FlatStoreSignedAtomicPat <FLAT_Pseudo inst, SDPatternOperator node,
10111011
ValueType vt, ValueType data_vt = vt> : GCNPat <
10121012
// atomic store follows atomic binop convention so the address comes
10131013
// first.
1014-
(node (GlobalOffset i64:$vaddr, i16:$offset), data_vt:$data),
1014+
(node (GlobalOffset i64:$vaddr, i32:$offset), data_vt:$data),
10151015
(inst $vaddr, getVregSrcForVT<data_vt>.ret:$data, $offset)
10161016
>;
10171017

@@ -1020,17 +1020,17 @@ multiclass FlatAtomicPat <string inst, string node, ValueType vt,
10201020
defvar rtnNode = !cast<PatFrags>(node#"_"#vt.Size);
10211021
defvar noRtnNode = !cast<PatFrags>(node#"_noret_"#vt.Size);
10221022

1023-
def : GCNPat <(vt (rtnNode (FlatOffset i64:$vaddr, i16:$offset), data_vt:$data)),
1023+
def : GCNPat <(vt (rtnNode (FlatOffset i64:$vaddr, i32:$offset), data_vt:$data)),
10241024
(!cast<FLAT_Pseudo>(inst#"_RTN") VReg_64:$vaddr, getVregSrcForVT<data_vt>.ret:$data, $offset)>;
10251025

10261026
let AddedComplexity = 1 in
1027-
def : GCNPat <(vt (noRtnNode (FlatOffset i64:$vaddr, i16:$offset), data_vt:$data)),
1027+
def : GCNPat <(vt (noRtnNode (FlatOffset i64:$vaddr, i32:$offset), data_vt:$data)),
10281028
(!cast<FLAT_Pseudo>(inst) VReg_64:$vaddr, getVregSrcForVT<data_vt>.ret:$data, $offset)>;
10291029
}
10301030

10311031
class FlatSignedAtomicPatBase <FLAT_Pseudo inst, SDPatternOperator node,
10321032
ValueType vt, ValueType data_vt = vt> : GCNPat <
1033-
(vt (node (GlobalOffset i64:$vaddr, i16:$offset), data_vt:$data)),
1033+
(vt (node (GlobalOffset i64:$vaddr, i32:$offset), data_vt:$data)),
10341034
(inst VReg_64:$vaddr, getVregSrcForVT<data_vt>.ret:$data, $offset)
10351035
>;
10361036

@@ -1063,49 +1063,49 @@ multiclass FlatSignedAtomicPatWithAddrSpace<string inst, string intr, string add
10631063
}
10641064

10651065
class ScratchLoadSignedPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat <
1066-
(vt (node (ScratchOffset (i32 VGPR_32:$vaddr), i16:$offset))),
1066+
(vt (node (ScratchOffset (i32 VGPR_32:$vaddr), i32:$offset))),
10671067
(inst $vaddr, $offset)
10681068
>;
10691069

10701070
class ScratchLoadSignedPat_D16 <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat <
1071-
(node (ScratchOffset (i32 VGPR_32:$vaddr), i16:$offset), vt:$in),
1071+
(node (ScratchOffset (i32 VGPR_32:$vaddr), i32:$offset), vt:$in),
10721072
(inst $vaddr, $offset, 0, $in)
10731073
>;
10741074

10751075
class ScratchStoreSignedPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat <
1076-
(node vt:$data, (ScratchOffset (i32 VGPR_32:$vaddr), i16:$offset)),
1076+
(node vt:$data, (ScratchOffset (i32 VGPR_32:$vaddr), i32:$offset)),
10771077
(inst getVregSrcForVT<vt>.ret:$data, $vaddr, $offset)
10781078
>;
10791079

10801080
class ScratchLoadSaddrPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat <
1081-
(vt (node (ScratchSAddr (i32 SGPR_32:$saddr), i16:$offset))),
1081+
(vt (node (ScratchSAddr (i32 SGPR_32:$saddr), i32:$offset))),
10821082
(inst $saddr, $offset)
10831083
>;
10841084

10851085
class ScratchLoadSaddrPat_D16 <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat <
1086-
(vt (node (ScratchSAddr (i32 SGPR_32:$saddr), i16:$offset), vt:$in)),
1086+
(vt (node (ScratchSAddr (i32 SGPR_32:$saddr), i32:$offset), vt:$in)),
10871087
(inst $saddr, $offset, 0, $in)
10881088
>;
10891089

10901090
class ScratchStoreSaddrPat <FLAT_Pseudo inst, SDPatternOperator node,
10911091
ValueType vt> : GCNPat <
1092-
(node vt:$data, (ScratchSAddr (i32 SGPR_32:$saddr), i16:$offset)),
1092+
(node vt:$data, (ScratchSAddr (i32 SGPR_32:$saddr), i32:$offset)),
10931093
(inst getVregSrcForVT<vt>.ret:$data, $saddr, $offset)
10941094
>;
10951095

10961096
class ScratchLoadSVaddrPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat <
1097-
(vt (node (ScratchSVAddr (i32 VGPR_32:$vaddr), (i32 SGPR_32:$saddr), i16:$offset))),
1097+
(vt (node (ScratchSVAddr (i32 VGPR_32:$vaddr), (i32 SGPR_32:$saddr), i32:$offset))),
10981098
(inst $vaddr, $saddr, $offset, 0)
10991099
>;
11001100

11011101
class ScratchStoreSVaddrPat <FLAT_Pseudo inst, SDPatternOperator node,
11021102
ValueType vt> : GCNPat <
1103-
(node vt:$data, (ScratchSVAddr (i32 VGPR_32:$vaddr), (i32 SGPR_32:$saddr), i16:$offset)),
1103+
(node vt:$data, (ScratchSVAddr (i32 VGPR_32:$vaddr), (i32 SGPR_32:$saddr), i32:$offset)),
11041104
(inst getVregSrcForVT<vt>.ret:$data, $vaddr, $saddr, $offset)
11051105
>;
11061106

11071107
class ScratchLoadSVaddrPat_D16 <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat <
1108-
(vt (node (ScratchSVAddr (i32 VGPR_32:$vaddr), (i32 SGPR_32:$saddr), i16:$offset), vt:$in)),
1108+
(vt (node (ScratchSVAddr (i32 VGPR_32:$vaddr), (i32 SGPR_32:$saddr), i32:$offset), vt:$in)),
11091109
(inst $vaddr, $saddr, $offset, 0, $in)
11101110
>;
11111111

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

Lines changed: 3 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -141,15 +141,10 @@ void AMDGPUInstPrinter::printFlatOffset(const MCInst *MI, unsigned OpNo,
141141
bool IsFlatSeg = !(Desc.TSFlags &
142142
(SIInstrFlags::FlatGlobal | SIInstrFlags::FlatScratch));
143143

144-
if (IsFlatSeg) { // Unsigned offset
144+
if (IsFlatSeg) // Unsigned offset
145145
printU16ImmDecOperand(MI, OpNo, O);
146-
} else { // Signed offset
147-
if (AMDGPU::isGFX10(STI)) {
148-
O << formatDec(SignExtend32<12>(MI->getOperand(OpNo).getImm()));
149-
} else {
150-
O << formatDec(SignExtend32<13>(MI->getOperand(OpNo).getImm()));
151-
}
152-
}
146+
else // Signed offset
147+
O << formatDec(SignExtend32(Imm, AMDGPU::getNumFlatOffsetBits(STI)));
153148
}
154149
}
155150

‎llvm/lib/Target/AMDGPU/SIInstrInfo.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1229,7 +1229,7 @@ class NamedOperandU32Default1<string Name, AsmOperandClass MatchClass> :
12291229

12301230
let OperandType = "OPERAND_IMMEDIATE" in {
12311231

1232-
def flat_offset : CustomOperand<i16, 1, "FlatOffset">;
1232+
def flat_offset : CustomOperand<i32, 1, "FlatOffset">;
12331233
def offset : NamedIntOperand<i16, "offset", "Offset">;
12341234
def offset0 : NamedIntOperand<i8, "offset0", "Offset0">;
12351235
def offset1 : NamedIntOperand<i8, "offset1", "Offset1">;

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