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[RISCV] Add subtarget features for profiles
This may simplify the usage of tools like `opt`, `llc`, etc. Reviewers: michaelmaitland, 4vtomat, preames, asb Reviewed By: michaelmaitland, preames, 4vtomat Pull Request: #84877
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‎llvm/lib/Target/RISCV/RISCV.td

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include "RISCVFeatures.td"
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//===----------------------------------------------------------------------===//
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// RISC-V profiles supported.
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//===----------------------------------------------------------------------===//
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include "RISCVProfiles.td"
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//===----------------------------------------------------------------------===//
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// Named operands for CSR instructions.
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//===----------------------------------------------------------------------===//

‎llvm/lib/Target/RISCV/RISCVProfiles.td

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//===------ RISCVProfiles.td - RISC-V Profiles -------------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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class RISCVProfile<string name, list<SubtargetFeature> features>
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: SubtargetFeature<name, "Is" # NAME, "true",
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"RISC-V " # name # " profile", features>;
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defvar RVI20U32Features = [Feature32Bit, FeatureStdExtI];
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defvar RVI20U64Features = [Feature64Bit, FeatureStdExtI];
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defvar RVA20U64Features = [Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC,
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FeatureStdExtZicntr,
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FeatureStdExtZiccif,
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FeatureStdExtZiccrse,
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FeatureStdExtZiccamoa,
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FeatureStdExtZa128rs,
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FeatureStdExtZicclsm];
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defvar RVA20S64Features = !listconcat(RVA20U64Features,
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[FeatureStdExtZifencei,
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FeatureStdExtSvbare,
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FeatureStdExtSvade,
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FeatureStdExtSsccptr,
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FeatureStdExtSstvecd,
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FeatureStdExtSstvala]);
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defvar RVA22U64Features = [Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC,
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FeatureStdExtZicntr,
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FeatureStdExtZiccif,
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FeatureStdExtZiccrse,
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FeatureStdExtZiccamoa,
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FeatureStdExtZicclsm,
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FeatureStdExtZa64rs,
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FeatureStdExtZihpm,
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FeatureStdExtZihintpause,
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FeatureStdExtZba,
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FeatureStdExtZbb,
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FeatureStdExtZbs,
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FeatureStdExtZic64b,
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FeatureStdExtZicbom,
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FeatureStdExtZicbop,
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FeatureStdExtZicboz,
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FeatureStdExtZfhmin,
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FeatureStdExtZkt];
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defvar RVA22S64Features = !listconcat(RVA22U64Features,
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[FeatureStdExtZifencei,
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FeatureStdExtSvbare,
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FeatureStdExtSvade,
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FeatureStdExtSsccptr,
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FeatureStdExtSstvecd,
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FeatureStdExtSstvala,
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FeatureStdExtSscounterenw,
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FeatureStdExtSvpbmt,
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FeatureStdExtSvinval]);
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defvar RVA23U64Features = [Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC,
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FeatureStdExtZicntr,
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FeatureStdExtZihpm,
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FeatureStdExtZiccif,
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FeatureStdExtZiccrse,
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FeatureStdExtZiccamoa,
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FeatureStdExtZicclsm,
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FeatureStdExtZa64rs,
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FeatureStdExtZihintpause,
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FeatureStdExtZba,
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FeatureStdExtZbb,
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FeatureStdExtZbs,
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FeatureStdExtZic64b,
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FeatureStdExtZicbom,
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FeatureStdExtZicbop,
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FeatureStdExtZicboz,
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FeatureStdExtZfhmin,
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FeatureStdExtZkt,
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FeatureStdExtV,
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FeatureStdExtZvfhmin,
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FeatureStdExtZvbb,
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FeatureStdExtZvkt,
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FeatureStdExtZihintntl,
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FeatureStdExtZicond,
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FeatureStdExtZimop,
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FeatureStdExtZcmop,
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FeatureStdExtZcb,
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FeatureStdExtZfa,
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FeatureStdExtZawrs];
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defvar RVA23S64Features = !listconcat(RVA23U64Features,
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[FeatureStdExtZifencei,
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FeatureStdExtSvbare,
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FeatureStdExtSvade,
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FeatureStdExtSsccptr,
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FeatureStdExtSstvecd,
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FeatureStdExtSstvala,
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FeatureStdExtSscounterenw,
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FeatureStdExtSvpbmt,
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FeatureStdExtSvinval,
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FeatureStdExtSvnapot,
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FeatureStdExtSstc,
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FeatureStdExtSscofpmf,
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FeatureStdExtSsnpm,
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FeatureStdExtSsu64xl,
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FeatureStdExtH,
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FeatureStdExtSsstateen,
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FeatureStdExtShcounterenw,
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FeatureStdExtShvstvala,
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FeatureStdExtShtvala,
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FeatureStdExtShvstvecd,
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FeatureStdExtShvsatpa,
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FeatureStdExtShgatpa]);
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defvar RVB23U64Features = [Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC,
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FeatureStdExtZicntr,
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FeatureStdExtZihpm,
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FeatureStdExtZiccif,
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FeatureStdExtZiccrse,
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FeatureStdExtZiccamoa,
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FeatureStdExtZicclsm,
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FeatureStdExtZa64rs,
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FeatureStdExtZihintpause,
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FeatureStdExtZba,
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FeatureStdExtZbb,
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FeatureStdExtZbs,
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FeatureStdExtZic64b,
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FeatureStdExtZicbom,
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FeatureStdExtZicbop,
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FeatureStdExtZicboz,
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FeatureStdExtZkt,
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FeatureStdExtZihintntl,
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FeatureStdExtZicond,
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FeatureStdExtZimop,
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FeatureStdExtZcmop,
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FeatureStdExtZcb,
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FeatureStdExtZfa,
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FeatureStdExtZawrs];
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defvar RVB23S64Features = !listconcat(RVB23U64Features,
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[FeatureStdExtZifencei,
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FeatureStdExtSvnapot,
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FeatureStdExtSvbare,
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FeatureStdExtSvade,
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FeatureStdExtSsccptr,
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FeatureStdExtSstvecd,
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FeatureStdExtSstvala,
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FeatureStdExtSscounterenw,
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FeatureStdExtSvpbmt,
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FeatureStdExtSvinval,
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FeatureStdExtSstc,
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FeatureStdExtSscofpmf,
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FeatureStdExtSsu64xl]);
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defvar RVM23U32Features = [Feature32Bit,
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FeatureStdExtI,
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FeatureStdExtM,
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FeatureStdExtZba,
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FeatureStdExtZbb,
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FeatureStdExtZbs,
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FeatureStdExtZicond,
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FeatureStdExtZihintpause,
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FeatureStdExtZihintntl,
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FeatureStdExtZce,
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FeatureStdExtZicbop,
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FeatureStdExtZimop,
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FeatureStdExtZcmop];
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def RVI20U32 : RISCVProfile<"rvi20u32", RVI20U32Features>;
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def RVI20U64 : RISCVProfile<"rvi20u64", RVI20U64Features>;
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def RVA20U64 : RISCVProfile<"rva20u64", RVA20U64Features>;
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def RVA20S64 : RISCVProfile<"rva20s64", RVA20S64Features>;
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def RVA22U64 : RISCVProfile<"rva22u64", RVA22U64Features>;
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def RVA22S64 : RISCVProfile<"rva22s64", RVA22S64Features>;
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def RVA23U64 : RISCVProfile<"rva23u64", RVA23U64Features>;
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def RVA23S64 : RISCVProfile<"rva23s64", RVA23S64Features>;
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def RVB23U64 : RISCVProfile<"rvb23u64", RVB23U64Features>;
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def RVB23S64 : RISCVProfile<"rvb23s64", RVB23S64Features>;
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def RVM23U32 : RISCVProfile<"rvm23u32", RVM23U32Features>;

‎llvm/test/CodeGen/RISCV/attributes.ll

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; RUN: llc -mtriple=riscv64 -mattr=+experimental-supm %s -o - | FileCheck --check-prefix=RV64SUPM %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssqosid %s -o - | FileCheck --check-prefix=RV64SSQOSID %s
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; Tests for profile features.
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; RUN: llc -mtriple=riscv32 -mattr=+rvi20u32 %s -o - | FileCheck --check-prefix=RVI20U32 %s
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; RUN: llc -mtriple=riscv64 -mattr=+rvi20u64 %s -o - | FileCheck --check-prefix=RVI20U64 %s
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; RUN: llc -mtriple=riscv64 -mattr=+rva20u64 %s -o - | FileCheck --check-prefix=RVA20U64 %s
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; RUN: llc -mtriple=riscv64 -mattr=+rva20s64 %s -o - | FileCheck --check-prefix=RVA20S64 %s
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; RUN: llc -mtriple=riscv64 -mattr=+rva22u64 %s -o - | FileCheck --check-prefix=RVA22U64 %s
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; RUN: llc -mtriple=riscv64 -mattr=+rva22s64 %s -o - | FileCheck --check-prefix=RVA22S64 %s
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; RUN: llc -mtriple=riscv64 -mattr=+rva23u64 %s -o - | FileCheck --check-prefix=RVA23U64 %s
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; RUN: llc -mtriple=riscv64 -mattr=+rva23s64 %s -o - | FileCheck --check-prefix=RVA23S64 %s
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; RUN: llc -mtriple=riscv64 -mattr=+rvb23u64 %s -o - | FileCheck --check-prefix=RVB23U64 %s
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; RUN: llc -mtriple=riscv64 -mattr=+rvb23s64 %s -o - | FileCheck --check-prefix=RVB23S64 %s
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; RUN: llc -mtriple=riscv32 -mattr=+rvm23u32 %s -o - | FileCheck --check-prefix=RVM23U32 %s
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; CHECK: .attribute 4, 16
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; RV32M: .attribute 5, "rv32i2p1_m2p0"
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; RV64SUPM: .attribute 5, "rv64i2p1_supm0p8"
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; RV64SSQOSID: .attribute 5, "rv64i2p1_ssqosid1p0"
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; RVI20U32: .attribute 5, "rv32i2p1"
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; RVI20U64: .attribute 5, "rv64i2p1"
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; RVA20U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_za128rs1p0"
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; RVA20S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zifencei2p0_za128rs1p0_ssccptr1p0_sstvala1p0_sstvecd1p0_svade1p0_svbare1p0"
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; RVA22U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zihintpause2p0_zihpm2p0_za64rs1p0_zfhmin1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0"
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; RVA22S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zifencei2p0_zihintpause2p0_zihpm2p0_za64rs1p0_zfhmin1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccptr1p0_sscounterenw1p0_sstvala1p0_sstvecd1p0_svade1p0_svbare1p0_svinval1p0_svpbmt1p0"
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; RVA23U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_za64rs1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
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; RVA23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_h1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_za64rs1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_ssnpm0p8_ssstateen1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0"
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; RVB23U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_za64rs1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0"
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; RVB23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_za64rs1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0"
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; RVM23U32: .attribute 5, "rv32i2p1_m2p0_zicbop1p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zimop1p0_zca1p0_zcb1p0_zce1p0_zcmop1p0_zcmp1p0_zcmt1p0_zba1p0_zbb1p0_zbs1p0"
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define i32 @addi(i32 %a) {
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%1 = add i32 %a, 1
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ret i32 %1

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