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[RISCV] Define vector vfwadd/vfwsub intrinsics.
Define vector vfwadd/vfwsub intrinsics and lower them to V instructions. We work with @rogfer01 from BSC to come out this patch. Authored-by: Roger Ferrer Ibanez <[email protected]> Co-Authored-by: Hsiangkai Wang <[email protected]> Differential Revision: https://reviews.llvm.org/D93583
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‎llvm/include/llvm/IR/IntrinsicsRISCV.td

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -388,6 +388,11 @@ let TargetPrefix = "riscv" in {
388388
defm vfsub : RISCVBinaryAAX;
389389
defm vfrsub : RISCVBinaryAAX;
390390

391+
defm vfwadd : RISCVBinaryABX;
392+
defm vfwsub : RISCVBinaryABX;
393+
defm vfwadd_w : RISCVBinaryAAX;
394+
defm vfwsub_w : RISCVBinaryAAX;
395+
391396
defm vsaddu : RISCVSaturatingBinaryAAX;
392397
defm vsadd : RISCVSaturatingBinaryAAX;
393398
defm vssubu : RISCVSaturatingBinaryAAX;

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Lines changed: 98 additions & 54 deletions
Original file line numberDiff line numberDiff line change
@@ -201,6 +201,19 @@ defset list<VTypeInfoToWide> AllWidenableIntVectors = {
201201
def : VTypeInfoToWide<VI32M4, VI64M8>;
202202
}
203203

204+
defset list<VTypeInfoToWide> AllWidenableFloatVectors = {
205+
def : VTypeInfoToWide<VF16MF4, VF32MF2>;
206+
def : VTypeInfoToWide<VF16MF2, VF32M1>;
207+
def : VTypeInfoToWide<VF16M1, VF32M2>;
208+
def : VTypeInfoToWide<VF16M2, VF32M4>;
209+
def : VTypeInfoToWide<VF16M4, VF32M8>;
210+
211+
def : VTypeInfoToWide<VF32MF2, VF64M1>;
212+
def : VTypeInfoToWide<VF32M1, VF64M2>;
213+
def : VTypeInfoToWide<VF32M2, VF64M4>;
214+
def : VTypeInfoToWide<VF32M4, VF64M8>;
215+
}
216+
204217
// This class holds the record of the RISCVVPseudoTable below.
205218
// This represents the information we need in codegen for each pseudo.
206219
// The definition should be consistent with `struct PseudoInfo` in
@@ -662,9 +675,10 @@ multiclass VPseudoBinaryW_VV {
662675
"@earlyclobber $rd">;
663676
}
664677

665-
multiclass VPseudoBinaryW_VX {
678+
multiclass VPseudoBinaryW_VX<bit IsFloat> {
666679
foreach m = MxList.m[0-5] in
667-
defm _VX : VPseudoBinary<m.wvrclass, m.vrclass, GPR, m,
680+
defm !if(!eq(IsFloat, 0), "_VX", "_VF") : VPseudoBinary<m.wvrclass, m.vrclass,
681+
!if(!eq(IsFloat, 0), GPR, FPR32), m,
668682
"@earlyclobber $rd">;
669683
}
670684

@@ -674,9 +688,10 @@ multiclass VPseudoBinaryW_WV {
674688
"@earlyclobber $rd">;
675689
}
676690

677-
multiclass VPseudoBinaryW_WX {
691+
multiclass VPseudoBinaryW_WX<bit IsFloat> {
678692
foreach m = MxList.m[0-5] in
679-
defm _WX : VPseudoBinary<m.wvrclass, m.wvrclass, GPR, m,
693+
defm !if(!eq(IsFloat, 0), "_WX", "_WF") : VPseudoBinary<m.wvrclass, m.wvrclass,
694+
!if(!eq(IsFloat, 0), GPR, FPR32), m,
680695
"@earlyclobber $rd">;
681696
}
682697

@@ -757,14 +772,14 @@ multiclass VPseudoBinaryV_VX_VI<Operand ImmType = simm5> {
757772
defm "" : VPseudoBinaryV_VI<ImmType>;
758773
}
759774

760-
multiclass VPseudoBinaryW_VV_VX {
775+
multiclass VPseudoBinaryW_VV_VX<bit IsFloat = 0> {
761776
defm "" : VPseudoBinaryW_VV;
762-
defm "" : VPseudoBinaryW_VX;
777+
defm "" : VPseudoBinaryW_VX<IsFloat>;
763778
}
764779

765-
multiclass VPseudoBinaryW_WV_WX {
780+
multiclass VPseudoBinaryW_WV_WX<bit IsFloat = 0> {
766781
defm "" : VPseudoBinaryW_WV;
767-
defm "" : VPseudoBinaryW_WX;
782+
defm "" : VPseudoBinaryW_WX<IsFloat>;
768783
}
769784

770785
multiclass VPseudoBinaryV_VM_XM_IM {
@@ -1120,8 +1135,9 @@ multiclass VPatBinaryV_VI<string intrinsic, string instruction,
11201135
vti.RegClass, imm_type>;
11211136
}
11221137

1123-
multiclass VPatBinaryW_VV<string intrinsic, string instruction> {
1124-
foreach VtiToWti = AllWidenableIntVectors in {
1138+
multiclass VPatBinaryW_VV<string intrinsic, string instruction,
1139+
list<VTypeInfoToWide> vtilist> {
1140+
foreach VtiToWti = vtilist in {
11251141
defvar Vti = VtiToWti.Vti;
11261142
defvar Wti = VtiToWti.Wti;
11271143
defm : VPatBinary<intrinsic, instruction, "VV",
@@ -1131,19 +1147,22 @@ multiclass VPatBinaryW_VV<string intrinsic, string instruction> {
11311147
}
11321148
}
11331149

1134-
multiclass VPatBinaryW_VX<string intrinsic, string instruction> {
1135-
foreach VtiToWti = AllWidenableIntVectors in {
1150+
multiclass VPatBinaryW_VX<string intrinsic, string instruction,
1151+
list<VTypeInfoToWide> vtilist> {
1152+
foreach VtiToWti = vtilist in {
11361153
defvar Vti = VtiToWti.Vti;
11371154
defvar Wti = VtiToWti.Wti;
1138-
defm : VPatBinary<intrinsic, instruction, "VX",
1139-
Wti.Vector, Vti.Vector, XLenVT, Vti.Mask,
1155+
defm : VPatBinary<intrinsic, instruction,
1156+
!if(!eq(Vti.Scalar, XLenVT), "VX", "VF"),
1157+
Wti.Vector, Vti.Vector, Vti.Scalar, Vti.Mask,
11401158
Vti.SEW, Vti.LMul, Wti.RegClass,
1141-
Vti.RegClass, GPR>;
1159+
Vti.RegClass, Vti.ScalarRegClass>;
11421160
}
11431161
}
11441162

1145-
multiclass VPatBinaryW_WV<string intrinsic, string instruction> {
1146-
foreach VtiToWti = AllWidenableIntVectors in {
1163+
multiclass VPatBinaryW_WV<string intrinsic, string instruction,
1164+
list<VTypeInfoToWide> vtilist> {
1165+
foreach VtiToWti = vtilist in {
11471166
defvar Vti = VtiToWti.Vti;
11481167
defvar Wti = VtiToWti.Wti;
11491168
defm : VPatBinary<intrinsic, instruction, "WV",
@@ -1153,19 +1172,22 @@ multiclass VPatBinaryW_WV<string intrinsic, string instruction> {
11531172
}
11541173
}
11551174

1156-
multiclass VPatBinaryW_WX<string intrinsic, string instruction> {
1157-
foreach VtiToWti = AllWidenableIntVectors in {
1175+
multiclass VPatBinaryW_WX<string intrinsic, string instruction,
1176+
list<VTypeInfoToWide> vtilist> {
1177+
foreach VtiToWti = vtilist in {
11581178
defvar Vti = VtiToWti.Vti;
11591179
defvar Wti = VtiToWti.Wti;
1160-
defm : VPatBinary<intrinsic, instruction, "WX",
1161-
Wti.Vector, Wti.Vector, XLenVT, Vti.Mask,
1180+
defm : VPatBinary<intrinsic, instruction,
1181+
!if(!eq(Vti.Scalar, XLenVT), "WX", "WF"),
1182+
Wti.Vector, Wti.Vector, Vti.Scalar, Vti.Mask,
11621183
Vti.SEW, Vti.LMul, Wti.RegClass,
1163-
Wti.RegClass, GPR>;
1184+
Wti.RegClass, Vti.ScalarRegClass>;
11641185
}
11651186
}
11661187

1167-
multiclass VPatBinaryV_WV<string intrinsic, string instruction> {
1168-
foreach VtiToWti = AllWidenableIntVectors in {
1188+
multiclass VPatBinaryV_WV<string intrinsic, string instruction,
1189+
list<VTypeInfoToWide> vtilist> {
1190+
foreach VtiToWti = vtilist in {
11691191
defvar Vti = VtiToWti.Vti;
11701192
defvar Wti = VtiToWti.Wti;
11711193
defm : VPatBinary<intrinsic, instruction, "WV",
@@ -1175,19 +1197,22 @@ multiclass VPatBinaryV_WV<string intrinsic, string instruction> {
11751197
}
11761198
}
11771199

1178-
multiclass VPatBinaryV_WX<string intrinsic, string instruction> {
1179-
foreach VtiToWti = AllWidenableIntVectors in {
1200+
multiclass VPatBinaryV_WX<string intrinsic, string instruction,
1201+
list<VTypeInfoToWide> vtilist> {
1202+
foreach VtiToWti = vtilist in {
11801203
defvar Vti = VtiToWti.Vti;
11811204
defvar Wti = VtiToWti.Wti;
1182-
defm : VPatBinary<intrinsic, instruction, "WX",
1183-
Vti.Vector, Wti.Vector, XLenVT, Vti.Mask,
1205+
defm : VPatBinary<intrinsic, instruction,
1206+
!if(!eq(Vti.Scalar, XLenVT), "WX", "WF"),
1207+
Vti.Vector, Wti.Vector, Vti.Scalar, Vti.Mask,
11841208
Vti.SEW, Vti.LMul, Vti.RegClass,
1185-
Wti.RegClass, GPR>;
1209+
Wti.RegClass, Vti.ScalarRegClass>;
11861210
}
11871211
}
11881212

1189-
multiclass VPatBinaryV_WI<string intrinsic, string instruction> {
1190-
foreach VtiToWti = AllWidenableIntVectors in {
1213+
multiclass VPatBinaryV_WI<string intrinsic, string instruction,
1214+
list<VTypeInfoToWide> vtilist> {
1215+
foreach VtiToWti = vtilist in {
11911216
defvar Vti = VtiToWti.Vti;
11921217
defvar Wti = VtiToWti.Wti;
11931218
defm : VPatBinary<intrinsic, instruction, "WI",
@@ -1273,23 +1298,26 @@ multiclass VPatBinaryV_VX_VI<string intrinsic, string instruction,
12731298
defm "" : VPatBinaryV_VI<intrinsic, instruction, vtilist, simm5>;
12741299
}
12751300

1276-
multiclass VPatBinaryW_VV_VX<string intrinsic, string instruction>
1301+
multiclass VPatBinaryW_VV_VX<string intrinsic, string instruction,
1302+
list<VTypeInfoToWide> vtilist>
12771303
{
1278-
defm "" : VPatBinaryW_VV<intrinsic, instruction>;
1279-
defm "" : VPatBinaryW_VX<intrinsic, instruction>;
1304+
defm "" : VPatBinaryW_VV<intrinsic, instruction, vtilist>;
1305+
defm "" : VPatBinaryW_VX<intrinsic, instruction, vtilist>;
12801306
}
12811307

1282-
multiclass VPatBinaryW_WV_WX<string intrinsic, string instruction>
1308+
multiclass VPatBinaryW_WV_WX<string intrinsic, string instruction,
1309+
list<VTypeInfoToWide> vtilist>
12831310
{
1284-
defm "" : VPatBinaryW_WV<intrinsic, instruction>;
1285-
defm "" : VPatBinaryW_WX<intrinsic, instruction>;
1311+
defm "" : VPatBinaryW_WV<intrinsic, instruction, vtilist>;
1312+
defm "" : VPatBinaryW_WX<intrinsic, instruction, vtilist>;
12861313
}
12871314

1288-
multiclass VPatBinaryV_WV_WX_WI<string intrinsic, string instruction>
1315+
multiclass VPatBinaryV_WV_WX_WI<string intrinsic, string instruction,
1316+
list<VTypeInfoToWide> vtilist>
12891317
{
1290-
defm "" : VPatBinaryV_WV<intrinsic, instruction>;
1291-
defm "" : VPatBinaryV_WX<intrinsic, instruction>;
1292-
defm "" : VPatBinaryV_WI<intrinsic, instruction>;
1318+
defm "" : VPatBinaryV_WV<intrinsic, instruction, vtilist>;
1319+
defm "" : VPatBinaryV_WX<intrinsic, instruction, vtilist>;
1320+
defm "" : VPatBinaryV_WI<intrinsic, instruction, vtilist>;
12931321
}
12941322

12951323
multiclass VPatBinaryV_VM_XM_IM<string intrinsic, string instruction>
@@ -1500,6 +1528,14 @@ defm PseudoVFADD : VPseudoBinaryV_VV_VX</*IsFloat=*/1>;
15001528
defm PseudoVFSUB : VPseudoBinaryV_VV_VX</*IsFloat=*/1>;
15011529
defm PseudoVFRSUB : VPseudoBinaryV_VX</*IsFloat=*/1>;
15021530

1531+
//===----------------------------------------------------------------------===//
1532+
// 14.3. Vector Widening Floating-Point Add/Subtract Instructions
1533+
//===----------------------------------------------------------------------===//
1534+
defm PseudoVFWADD : VPseudoBinaryW_VV_VX</*IsFloat=*/1>;
1535+
defm PseudoVFWSUB : VPseudoBinaryW_VV_VX</*IsFloat=*/1>;
1536+
defm PseudoVFWADD : VPseudoBinaryW_WV_WX</*IsFloat=*/1>;
1537+
defm PseudoVFWSUB : VPseudoBinaryW_WV_WX</*IsFloat=*/1>;
1538+
15031539
//===----------------------------------------------------------------------===//
15041540
// 14.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
15051541
//===----------------------------------------------------------------------===//
@@ -1674,14 +1710,14 @@ defm "" : VPatBinaryV_VX_VI<"int_riscv_vrsub", "PseudoVRSUB", AllIntegerVectors>
16741710
//===----------------------------------------------------------------------===//
16751711
// 12.2. Vector Widening Integer Add/Subtract
16761712
//===----------------------------------------------------------------------===//
1677-
defm "" : VPatBinaryW_VV_VX<"int_riscv_vwaddu", "PseudoVWADDU">;
1678-
defm "" : VPatBinaryW_VV_VX<"int_riscv_vwsubu", "PseudoVWSUBU">;
1679-
defm "" : VPatBinaryW_VV_VX<"int_riscv_vwadd", "PseudoVWADD">;
1680-
defm "" : VPatBinaryW_VV_VX<"int_riscv_vwsub", "PseudoVWSUB">;
1681-
defm "" : VPatBinaryW_WV_WX<"int_riscv_vwaddu_w", "PseudoVWADDU">;
1682-
defm "" : VPatBinaryW_WV_WX<"int_riscv_vwsubu_w", "PseudoVWSUBU">;
1683-
defm "" : VPatBinaryW_WV_WX<"int_riscv_vwadd_w", "PseudoVWADD">;
1684-
defm "" : VPatBinaryW_WV_WX<"int_riscv_vwsub_w", "PseudoVWSUB">;
1713+
defm "" : VPatBinaryW_VV_VX<"int_riscv_vwaddu", "PseudoVWADDU", AllWidenableIntVectors>;
1714+
defm "" : VPatBinaryW_VV_VX<"int_riscv_vwsubu", "PseudoVWSUBU", AllWidenableIntVectors>;
1715+
defm "" : VPatBinaryW_VV_VX<"int_riscv_vwadd", "PseudoVWADD", AllWidenableIntVectors>;
1716+
defm "" : VPatBinaryW_VV_VX<"int_riscv_vwsub", "PseudoVWSUB", AllWidenableIntVectors>;
1717+
defm "" : VPatBinaryW_WV_WX<"int_riscv_vwaddu_w", "PseudoVWADDU", AllWidenableIntVectors>;
1718+
defm "" : VPatBinaryW_WV_WX<"int_riscv_vwsubu_w", "PseudoVWSUBU", AllWidenableIntVectors>;
1719+
defm "" : VPatBinaryW_WV_WX<"int_riscv_vwadd_w", "PseudoVWADD", AllWidenableIntVectors>;
1720+
defm "" : VPatBinaryW_WV_WX<"int_riscv_vwsub_w", "PseudoVWSUB", AllWidenableIntVectors>;
16851721

16861722
//===----------------------------------------------------------------------===//
16871723
// 12.4. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
@@ -1707,8 +1743,8 @@ defm "" : VPatBinaryV_VV_VX_VI<"int_riscv_vsra", "PseudoVSRA", AllIntegerVectors
17071743
//===----------------------------------------------------------------------===//
17081744
// 12.7. Vector Narrowing Integer Right Shift Instructions
17091745
//===----------------------------------------------------------------------===//
1710-
defm "" : VPatBinaryV_WV_WX_WI<"int_riscv_vnsrl", "PseudoVNSRL">;
1711-
defm "" : VPatBinaryV_WV_WX_WI<"int_riscv_vnsra", "PseudoVNSRA">;
1746+
defm "" : VPatBinaryV_WV_WX_WI<"int_riscv_vnsrl", "PseudoVNSRL", AllWidenableIntVectors>;
1747+
defm "" : VPatBinaryV_WV_WX_WI<"int_riscv_vnsra", "PseudoVNSRA", AllWidenableIntVectors>;
17121748

17131749
//===----------------------------------------------------------------------===//
17141750
// 12.9. Vector Integer Min/Max Instructions
@@ -1737,9 +1773,9 @@ defm "" : VPatBinaryV_VV_VX<"int_riscv_vrem", "PseudoVREM", AllIntegerVectors>;
17371773
//===----------------------------------------------------------------------===//
17381774
// 12.12. Vector Widening Integer Multiply Instructions
17391775
//===----------------------------------------------------------------------===//
1740-
defm "" : VPatBinaryW_VV_VX<"int_riscv_vwmul", "PseudoVWMUL">;
1741-
defm "" : VPatBinaryW_VV_VX<"int_riscv_vwmulu", "PseudoVWMULU">;
1742-
defm "" : VPatBinaryW_VV_VX<"int_riscv_vwmulsu", "PseudoVWMULSU">;
1776+
defm "" : VPatBinaryW_VV_VX<"int_riscv_vwmul", "PseudoVWMUL", AllWidenableIntVectors>;
1777+
defm "" : VPatBinaryW_VV_VX<"int_riscv_vwmulu", "PseudoVWMULU", AllWidenableIntVectors>;
1778+
defm "" : VPatBinaryW_VV_VX<"int_riscv_vwmulsu", "PseudoVWMULSU", AllWidenableIntVectors>;
17431779

17441780
//===----------------------------------------------------------------------===//
17451781
// 12.17. Vector Integer Move Instructions
@@ -1778,6 +1814,14 @@ defm "" : VPatBinaryV_VV_VX<"int_riscv_vfadd", "PseudoVFADD", AllFloatVectors>;
17781814
defm "" : VPatBinaryV_VV_VX<"int_riscv_vfsub", "PseudoVFSUB", AllFloatVectors>;
17791815
defm "" : VPatBinaryV_VX<"int_riscv_vfrsub", "PseudoVFRSUB", AllFloatVectors>;
17801816

1817+
//===----------------------------------------------------------------------===//
1818+
// 14.3. Vector Widening Floating-Point Add/Subtract Instructions
1819+
//===----------------------------------------------------------------------===//
1820+
defm "" : VPatBinaryW_VV_VX<"int_riscv_vfwadd", "PseudoVFWADD", AllWidenableFloatVectors>;
1821+
defm "" : VPatBinaryW_VV_VX<"int_riscv_vfwsub", "PseudoVFWSUB", AllWidenableFloatVectors>;
1822+
defm "" : VPatBinaryW_WV_WX<"int_riscv_vfwadd_w", "PseudoVFWADD", AllWidenableFloatVectors>;
1823+
defm "" : VPatBinaryW_WV_WX<"int_riscv_vfwsub_w", "PseudoVFWSUB", AllWidenableFloatVectors>;
1824+
17811825
//===----------------------------------------------------------------------===//
17821826
// 14.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
17831827
//===----------------------------------------------------------------------===//

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