@@ -211,10 +211,10 @@ static bool isMaskOperand(const MachineInstr &MI, const MachineOperand &MO,
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return Desc.operands ()[MO.getOperandNo ()].RegClass == RISCV::VMV0RegClassID;
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}
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- // / Return the OperandInfo for MO, which is an operand of MI.
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- static OperandInfo getOperandInfo (const MachineInstr &MI,
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- const MachineOperand &MO,
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+ // / Return the OperandInfo for MO.
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+ static OperandInfo getOperandInfo (const MachineOperand &MO,
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const MachineRegisterInfo *MRI) {
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+ const MachineInstr &MI = *MO.getParent ();
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const RISCVVPseudosTable::PseudoInfo *RVV =
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RISCVVPseudosTable::getPseudoInfo (MI.getOpcode ());
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assert (RVV && " Could not find MI in PseudoTable" );
@@ -942,8 +942,8 @@ bool RISCVVLOptimizer::checkUsers(const MachineOperand *&CommonVL,
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assert (isVectorRegClass (UserMI.getOperand (0 ).getReg (), MRI) &&
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" Expected DEF and USE to be vector registers" );
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- OperandInfo ConsumerInfo = getOperandInfo (UserMI, UserOp, MRI);
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- OperandInfo ProducerInfo = getOperandInfo (MI, MI .getOperand (0 ), MRI);
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+ OperandInfo ConsumerInfo = getOperandInfo (UserOp, MRI);
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+ OperandInfo ProducerInfo = getOperandInfo (MI.getOperand (0 ), MRI);
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if (ConsumerInfo.isUnknown () || ProducerInfo.isUnknown () ||
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!OperandInfo::EMULAndEEWAreEqual (ConsumerInfo, ProducerInfo)) {
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LLVM_DEBUG (dbgs () << " Abort due to incompatible or unknown "
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