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[DAGCombiner] Preserve nneg flag from inner zext when we combine (z/s/aext (zext X)) (#82199)
1 parent 1b26c25 commit f8cbb67

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3 files changed

+51
-66
lines changed

3 files changed

+51
-66
lines changed

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 13 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -13710,8 +13710,12 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
1371013710

1371113711
// fold (zext (zext x)) -> (zext x)
1371213712
// fold (zext (aext x)) -> (zext x)
13713-
if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
13714-
return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
13713+
if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
13714+
SDNodeFlags Flags;
13715+
if (N0.getOpcode() == ISD::ZERO_EXTEND)
13716+
Flags.setNonNeg(N0->getFlags().hasNonNeg());
13717+
return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0), Flags);
13718+
}
1371513719

1371613720
// fold (zext (aext_extend_vector_inreg x)) -> (zext_extend_vector_inreg x)
1371713721
// fold (zext (zext_extend_vector_inreg x)) -> (zext_extend_vector_inreg x)
@@ -14011,10 +14015,13 @@ SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
1401114015
// fold (aext (aext x)) -> (aext x)
1401214016
// fold (aext (zext x)) -> (zext x)
1401314017
// fold (aext (sext x)) -> (sext x)
14014-
if (N0.getOpcode() == ISD::ANY_EXTEND ||
14015-
N0.getOpcode() == ISD::ZERO_EXTEND ||
14016-
N0.getOpcode() == ISD::SIGN_EXTEND)
14017-
return DAG.getNode(N0.getOpcode(), DL, VT, N0.getOperand(0));
14018+
if (N0.getOpcode() == ISD::ANY_EXTEND || N0.getOpcode() == ISD::ZERO_EXTEND ||
14019+
N0.getOpcode() == ISD::SIGN_EXTEND) {
14020+
SDNodeFlags Flags;
14021+
if (N0.getOpcode() == ISD::ZERO_EXTEND)
14022+
Flags.setNonNeg(N0->getFlags().hasNonNeg());
14023+
return DAG.getNode(N0.getOpcode(), DL, VT, N0.getOperand(0), Flags);
14024+
}
1401814025

1401914026
// fold (aext (aext_extend_vector_inreg x)) -> (aext_extend_vector_inreg x)
1402014027
// fold (aext (zext_extend_vector_inreg x)) -> (zext_extend_vector_inreg x)

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 17 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -5715,8 +5715,12 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
57155715
N1.getValueType().getVectorElementCount()) &&
57165716
"Vector element count mismatch!");
57175717
assert(N1.getValueType().bitsLT(VT) && "Invalid sext node, dst < src!");
5718-
if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND)
5719-
return getNode(OpOpcode, DL, VT, N1.getOperand(0));
5718+
if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) {
5719+
SDNodeFlags Flags;
5720+
if (OpOpcode == ISD::ZERO_EXTEND)
5721+
Flags.setNonNeg(N1->getFlags().hasNonNeg());
5722+
return getNode(OpOpcode, DL, VT, N1.getOperand(0), Flags);
5723+
}
57205724
if (OpOpcode == ISD::UNDEF)
57215725
// sext(undef) = 0, because the top bits will all be the same.
57225726
return getConstant(0, DL, VT);
@@ -5732,8 +5736,11 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
57325736
N1.getValueType().getVectorElementCount()) &&
57335737
"Vector element count mismatch!");
57345738
assert(N1.getValueType().bitsLT(VT) && "Invalid zext node, dst < src!");
5735-
if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x)
5736-
return getNode(ISD::ZERO_EXTEND, DL, VT, N1.getOperand(0));
5739+
if (OpOpcode == ISD::ZERO_EXTEND) { // (zext (zext x)) -> (zext x)
5740+
SDNodeFlags Flags;
5741+
Flags.setNonNeg(N1->getFlags().hasNonNeg());
5742+
return getNode(ISD::ZERO_EXTEND, DL, VT, N1.getOperand(0), Flags);
5743+
}
57375744
if (OpOpcode == ISD::UNDEF)
57385745
// zext(undef) = 0, because the top bits will be zero.
57395746
return getConstant(0, DL, VT);
@@ -5769,9 +5776,13 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
57695776
assert(N1.getValueType().bitsLT(VT) && "Invalid anyext node, dst < src!");
57705777

57715778
if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND ||
5772-
OpOpcode == ISD::ANY_EXTEND)
5779+
OpOpcode == ISD::ANY_EXTEND) {
5780+
SDNodeFlags Flags;
5781+
if (OpOpcode == ISD::ZERO_EXTEND)
5782+
Flags.setNonNeg(N1->getFlags().hasNonNeg());
57735783
// (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x)
5774-
return getNode(OpOpcode, DL, VT, N1.getOperand(0));
5784+
return getNode(OpOpcode, DL, VT, N1.getOperand(0), Flags);
5785+
}
57755786
if (OpOpcode == ISD::UNDEF)
57765787
return getUNDEF(VT);
57775788

‎llvm/test/CodeGen/RISCV/sext-zext-trunc.ll

Lines changed: 21 additions & 54 deletions
Original file line numberDiff line numberDiff line change
@@ -791,24 +791,13 @@ define void @zext_nneg_dominating_icmp_i32(i16 signext %0) {
791791
; RV32I-NEXT: .LBB47_2:
792792
; RV32I-NEXT: ret
793793
;
794-
; RV64I-LABEL: zext_nneg_dominating_icmp_i32:
795-
; RV64I: # %bb.0:
796-
; RV64I-NEXT: bltz a0, .LBB47_2
797-
; RV64I-NEXT: # %bb.1:
798-
; RV64I-NEXT: slli a0, a0, 48
799-
; RV64I-NEXT: srli a0, a0, 48
800-
; RV64I-NEXT: tail bar_i32
801-
; RV64I-NEXT: .LBB47_2:
802-
; RV64I-NEXT: ret
803-
;
804-
; RV64ZBB-LABEL: zext_nneg_dominating_icmp_i32:
805-
; RV64ZBB: # %bb.0:
806-
; RV64ZBB-NEXT: bltz a0, .LBB47_2
807-
; RV64ZBB-NEXT: # %bb.1:
808-
; RV64ZBB-NEXT: zext.h a0, a0
809-
; RV64ZBB-NEXT: tail bar_i32
810-
; RV64ZBB-NEXT: .LBB47_2:
811-
; RV64ZBB-NEXT: ret
794+
; RV64-LABEL: zext_nneg_dominating_icmp_i32:
795+
; RV64: # %bb.0:
796+
; RV64-NEXT: bltz a0, .LBB47_2
797+
; RV64-NEXT: # %bb.1:
798+
; RV64-NEXT: tail bar_i32
799+
; RV64-NEXT: .LBB47_2:
800+
; RV64-NEXT: ret
812801
%2 = icmp sgt i16 %0, -1
813802
br i1 %2, label %3, label %5
814803

@@ -834,24 +823,13 @@ define void @zext_nneg_dominating_icmp_i32_signext(i16 signext %0) {
834823
; RV32I-NEXT: .LBB48_2:
835824
; RV32I-NEXT: ret
836825
;
837-
; RV64I-LABEL: zext_nneg_dominating_icmp_i32_signext:
838-
; RV64I: # %bb.0:
839-
; RV64I-NEXT: bltz a0, .LBB48_2
840-
; RV64I-NEXT: # %bb.1:
841-
; RV64I-NEXT: slli a0, a0, 48
842-
; RV64I-NEXT: srli a0, a0, 48
843-
; RV64I-NEXT: tail bar_i32
844-
; RV64I-NEXT: .LBB48_2:
845-
; RV64I-NEXT: ret
846-
;
847-
; RV64ZBB-LABEL: zext_nneg_dominating_icmp_i32_signext:
848-
; RV64ZBB: # %bb.0:
849-
; RV64ZBB-NEXT: bltz a0, .LBB48_2
850-
; RV64ZBB-NEXT: # %bb.1:
851-
; RV64ZBB-NEXT: zext.h a0, a0
852-
; RV64ZBB-NEXT: tail bar_i32
853-
; RV64ZBB-NEXT: .LBB48_2:
854-
; RV64ZBB-NEXT: ret
826+
; RV64-LABEL: zext_nneg_dominating_icmp_i32_signext:
827+
; RV64: # %bb.0:
828+
; RV64-NEXT: bltz a0, .LBB48_2
829+
; RV64-NEXT: # %bb.1:
830+
; RV64-NEXT: tail bar_i32
831+
; RV64-NEXT: .LBB48_2:
832+
; RV64-NEXT: ret
855833
%2 = icmp sgt i16 %0, -1
856834
br i1 %2, label %3, label %5
857835

@@ -875,24 +853,13 @@ define void @zext_nneg_dominating_icmp_i32_zeroext(i16 signext %0) {
875853
; RV32I-NEXT: .LBB49_2:
876854
; RV32I-NEXT: ret
877855
;
878-
; RV64I-LABEL: zext_nneg_dominating_icmp_i32_zeroext:
879-
; RV64I: # %bb.0:
880-
; RV64I-NEXT: bltz a0, .LBB49_2
881-
; RV64I-NEXT: # %bb.1:
882-
; RV64I-NEXT: slli a0, a0, 48
883-
; RV64I-NEXT: srli a0, a0, 48
884-
; RV64I-NEXT: tail bar_i32
885-
; RV64I-NEXT: .LBB49_2:
886-
; RV64I-NEXT: ret
887-
;
888-
; RV64ZBB-LABEL: zext_nneg_dominating_icmp_i32_zeroext:
889-
; RV64ZBB: # %bb.0:
890-
; RV64ZBB-NEXT: bltz a0, .LBB49_2
891-
; RV64ZBB-NEXT: # %bb.1:
892-
; RV64ZBB-NEXT: zext.h a0, a0
893-
; RV64ZBB-NEXT: tail bar_i32
894-
; RV64ZBB-NEXT: .LBB49_2:
895-
; RV64ZBB-NEXT: ret
856+
; RV64-LABEL: zext_nneg_dominating_icmp_i32_zeroext:
857+
; RV64: # %bb.0:
858+
; RV64-NEXT: bltz a0, .LBB49_2
859+
; RV64-NEXT: # %bb.1:
860+
; RV64-NEXT: tail bar_i32
861+
; RV64-NEXT: .LBB49_2:
862+
; RV64-NEXT: ret
896863
%2 = icmp sgt i16 %0, -1
897864
br i1 %2, label %3, label %5
898865

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