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[RegAlloc][NewPM] Plug Greedy RA in codegen pipeline
1 parent 516482f commit f93228a

15 files changed

+71
-14
lines changed

‎llvm/include/llvm/Passes/CodeGenPassBuilder.h

Lines changed: 17 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1059,7 +1059,7 @@ void CodeGenPassBuilder<Derived, TargetMachineT>::addMachineSSAOptimization(
10591059
///
10601060
/// A target that uses the standard regalloc pass order for fast or optimized
10611061
/// allocation may still override this for per-target regalloc
1062-
/// selection. But -regalloc=... always takes precedence.
1062+
/// selection. But -regalloc-npm=... always takes precedence.
10631063
template <typename Derived, typename TargetMachineT>
10641064
void CodeGenPassBuilder<Derived, TargetMachineT>::addTargetRegisterAllocator(
10651065
AddMachinePass &addPass, bool Optimized) const {
@@ -1076,6 +1076,22 @@ template <typename Derived, typename TargetMachineT>
10761076
void CodeGenPassBuilder<Derived, TargetMachineT>::addRegAllocPass(
10771077
AddMachinePass &addPass, bool Optimized) const {
10781078
// TODO: Parse Opt.RegAlloc to add register allocator.
1079+
// Use the specified -regalloc-npm={basic|greedy|fast|pbqp}
1080+
if (Opt.RegAlloc > RegAllocType::Default) {
1081+
switch (Opt.RegAlloc) {
1082+
case RegAllocType::Fast:
1083+
addPass(RegAllocFastPass());
1084+
break;
1085+
case RegAllocType::Greedy:
1086+
addPass(RAGreedyPass());
1087+
break;
1088+
default:
1089+
llvm_unreachable("Register allocator not supported yet.");
1090+
}
1091+
return;
1092+
}
1093+
// -regalloc=default or unspecified, so pick based on the optimization level.
1094+
derived().addTargetRegisterAllocator(addPass, Optimized);
10791095
}
10801096

10811097
template <typename Derived, typename TargetMachineT>

‎llvm/include/llvm/Passes/MachinePassRegistry.def

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -188,12 +188,12 @@ MACHINE_FUNCTION_PASS_WITH_PARAMS(
188188
},
189189
"filter=reg-filter;no-clear-vregs")
190190

191+
// 'all' is the default filter
191192
MACHINE_FUNCTION_PASS_WITH_PARAMS(
192193
"regallocgreedy", "RAGreedyPass",
193194
[](RAGreedyPass::Options Opts) { return RAGreedyPass(Opts); },
194195
[PB = this](StringRef Params) {
195-
// TODO: parseRegAllocGreedyFilterFunc(*PB, Params);
196-
return Expected<RAGreedyPass::Options>(RAGreedyPass::Options{});
196+
return parseRegAllocGreedyFilterFunc(*PB, Params);
197197
}, "reg-filter"
198198
)
199199
#undef MACHINE_FUNCTION_PASS_WITH_PARAMS

‎llvm/include/llvm/Target/CGPassBuilderOption.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,7 @@ struct CGPassBuilderOption {
5353
bool RequiresCodeGenSCCOrder = false;
5454

5555
RunOutliner EnableMachineOutliner = RunOutliner::TargetDefault;
56-
StringRef RegAlloc = "default";
56+
RegAllocType RegAlloc = RegAllocType::Default;
5757
std::optional<GlobalISelAbortMode> EnableGlobalISelAbort;
5858
std::string FSProfileFile;
5959
std::string FSRemappingFile;

‎llvm/lib/Passes/PassBuilder.cpp

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1315,6 +1315,19 @@ parseBoundsCheckingOptions(StringRef Params) {
13151315
return Mode;
13161316
}
13171317

1318+
Expected<RAGreedyPass::Options> parseRegAllocGreedyFilterFunc(PassBuilder &PB, StringRef Params) {
1319+
if (Params.empty() || Params == "all") {
1320+
return RAGreedyPass::Options();
1321+
}
1322+
std::optional<RegAllocFilterFunc> Filter = PB.parseRegAllocFilter(Params);
1323+
if (!Filter) {
1324+
return make_error<StringError>(
1325+
formatv("invalid regallocgreedy register filter '{0}' ", Params).str(),
1326+
inconvertibleErrorCode());
1327+
}
1328+
return RAGreedyPass::Options{*Filter, Params};
1329+
}
1330+
13181331
} // namespace
13191332

13201333
/// Tests whether a pass name starts with a valid prefix for a default pipeline

‎llvm/test/CodeGen/AArch64/implicit-def-remat-requires-impdef-check.mir

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
22
# RUN: llc -mtriple=arm64-apple-macosx -mcpu=apple-m1 -stress-regalloc=4 -verify-regalloc -run-pass=greedy -o - %s | FileCheck %s
3+
# RUN: llc -mtriple=arm64-apple-macosx -mcpu=apple-m1 -stress-regalloc=4 -verify-regalloc -passes=regallocgreedy -o - %s | FileCheck %s
34

45
--- |
56
define void @inst_stores_to_dead_spill_implicit_def_impdef() {

‎llvm/test/CodeGen/AArch64/implicit-def-with-impdef-greedy-assert.mir

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
22
# RUN: llc -mtriple=arm64-apple-ios -run-pass=greedy -o - %s | FileCheck %s
3+
# RUN: llc -mtriple=arm64-apple-ios -passes=regallocgreedy -o - %s | FileCheck %s
34

45
---
56
name: widget

‎llvm/test/CodeGen/AArch64/pr51516.mir

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,5 @@
11
# RUN: llc -mtriple=aarch64-unknown-fuchsia -run-pass=greedy -verify-machineinstrs -o - %s | FileCheck %s
2+
# RUN: llc -mtriple=aarch64-unknown-fuchsia -passes=regallocgreedy -verify-machineinstrs -o - %s | FileCheck %s
23

34
# Check that we spill %31 and do not rematerialize it since the use operand
45
# of ADDXri is killed by the STRXui in this block.

‎llvm/test/CodeGen/AArch64/spill-fold.mir

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,7 @@
11
# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass greedy -verify-machineinstrs -o - %s | FileCheck %s
22
# RUN: llc -mtriple=aarch64_be-none-linux-gnu -run-pass greedy -verify-machineinstrs -o - %s | FileCheck %s
3+
# RUN: llc -mtriple=aarch64-none-linux-gnu -passes=regallocgreedy -o - %s | FileCheck %s
4+
# RUN: llc -mtriple=aarch64_be-none-linux-gnu -passes=regallocgreedy -o - %s | FileCheck %s
35
--- |
46
define i64 @test_subreg_spill_fold() { ret i64 0 }
57
define i64 @test_subreg_spill_fold2() { ret i64 0 }

‎llvm/test/CodeGen/AMDGPU/extend-phi-subrange-not-in-parent.mir

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
22
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-regalloc -run-pass=greedy -o - %s | FileCheck %s
3+
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-regalloc -passes=regallocgreedy -o - %s | FileCheck %s
34

45
# Initially %2 starts out with 2 subranges (one for sub0, and one for
56
# the rest of the lanes). After %2 is split, after refineSubRanges the

‎llvm/test/CodeGen/MIR/Generic/runPass.mir

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@
22
# RUN: llc -run-pass=regallocbasic -debug-pass=Arguments -o - %s | FileCheck %s
33
# RUN: llc -run-pass=regallocfast -debug-pass=Arguments -o - %s | FileCheck %s
44
# RUN: llc -passes=regallocfast -o - %s | FileCheck %s
5+
# RUN: llc -passes=regallocgreedy -o - %s | FileCheck %s
56

67
# Check that passes are initialized correctly, so that it's possible to
78
# use -run-pass.

‎llvm/test/CodeGen/SystemZ/clear-liverange-spillreg.mir

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,5 @@
11
#RUN: llc -o - %s -mtriple=s390x-ibm-linux -run-pass=greedy
2+
#RUN: llc -o - %s -mtriple=s390x-ibm-linux -passes=regallocgreedy
23
#PR34502. Check HoistSpill works properly after the live range of spilled
34
#virtual register is cleared.
45
--- |

‎llvm/test/CodeGen/Thumb/high-reg-clobber.mir

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33
# RUN: llc -mtriple thumbv6m-arm-none-eabi -run-pass greedy %s -o - | FileCheck %s
44
# RUN: llc -mtriple thumbv6m-arm-none-eabi -run-pass regallocfast %s -o - | FileCheck %s --check-prefix=FAST
55
# RUN: llc -mtriple thumbv6m-arm-none-eabi -passes=regallocfast %s -o - | FileCheck %s --check-prefix=FAST
6+
# RUN: llc -mtriple thumbv6m-arm-none-eabi -passes=regallocgreedy %s -o - | FileCheck %s
67

78
...
89
---

‎llvm/test/CodeGen/X86/limit-split-cost.mir

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
# REQUIRES: asserts
22
# RUN: llc -mtriple=x86_64-- -run-pass=greedy %s -debug-only=regalloc -huge-size-for-split=0 -o /dev/null 2>&1 | FileCheck %s
3+
# RUN: llc -mtriple=x86_64-- -passes=regallocgreedy %s -debug-only=regalloc -huge-size-for-split=0 -o /dev/null 2>&1 | FileCheck %s
34
# Check no global region split is needed because the live range to split is trivially rematerializable.
45
# CHECK-NOT: Compact region bundles
56
--- |

‎llvm/test/tools/llc/new-pm/regalloc-amdgpu.mir

Lines changed: 11 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,17 @@
11
# REQUIRES: amdgpu-registered-target
2-
# RUN: llc -mtriple=amdgcn --passes='regallocfast<filter=sgpr>,regallocfast<filter=wwm>,regallocfast<filter=vgpr>' --print-pipeline-passes --filetype=null %s | FileCheck %s --check-prefix=PASS
3-
# RUN: not llc -mtriple=amdgcn --passes='regallocfast<filter=bad-filter>' --print-pipeline-passes --filetype=null %s 2>&1 | FileCheck %s --check-prefix=BAD-FILTER
2+
# RUN: llc -mtriple=amdgcn --passes='regallocfast<filter=sgpr>,regallocfast<filter=wwm>,regallocfast<filter=vgpr>' --print-pipeline-passes --filetype=null %s | FileCheck %s --check-prefix=RAFAST
3+
# RUN: not llc -mtriple=amdgcn --passes='regallocfast<filter=bad-filter>' --print-pipeline-passes --filetype=null %s 2>&1 | FileCheck %s --check-prefix=RAFAST-BAD-FILTER
44

5-
# PASS: regallocfast<filter=sgpr>
6-
# PASS: regallocfast<filter=wwm>
7-
# PASS: regallocfast<filter=vgpr>
8-
# BAD-FILTER: invalid regallocfast register filter 'bad-filter'
5+
# RUN: llc -mtriple=amdgcn -passes='regallocgreedy<sgpr>' --print-pipeline-passes --filetype=null %s | FileCheck %s --check-prefix=RAGREEDY
6+
# RUN: not llc -mtriple=amdgcn -passes='regallocgreedy<bad-filter>' --print-pipeline-passes --filetype=null %s 2>&1 | FileCheck %s --check-prefix=RAGREEDY-BAD-FILTER
97

8+
# RAFAST: regallocfast<filter=sgpr>
9+
# RAFAST: regallocfast<filter=wwm>
10+
# RAFAST: regallocfast<filter=vgpr>
11+
# RAFAST-BAD-FILTER: invalid regallocfast register filter 'bad-filter'
12+
13+
# RAGREEDY: regallocgreedy<sgpr>
14+
# RAGREEDY-BAD-FILTER: invalid regallocgreedy register filter 'bad-filter'
1015
---
1116
name: f
1217
...

‎llvm/tools/llc/NewPMDriver.cpp

Lines changed: 17 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -48,10 +48,23 @@
4848

4949
using namespace llvm;
5050

51-
static cl::opt<std::string>
52-
RegAlloc("regalloc-npm",
53-
cl::desc("Register allocator to use for new pass manager"),
54-
cl::Hidden, cl::init("default"));
51+
// static cl::opt<std::string>
52+
// RegAlloc("regalloc-npm",
53+
// cl::desc("Register allocator to use for new pass manager"),
54+
// cl::Hidden, cl::init("default"));
55+
56+
// create option for RegAllocType enum
57+
static cl::opt<RegAllocType> RegAlloc(
58+
"regalloc-npm", cl::desc("Register allocator to use for new pass manager"),
59+
cl::Hidden, cl::init(RegAllocType::Default),
60+
cl::values(
61+
clEnumValN(RegAllocType::Default, "default",
62+
"Default register allocator"),
63+
clEnumValN(RegAllocType::PBQP, "pbqp", "PBQP register allocator"),
64+
clEnumValN(RegAllocType::Fast, "fast", "Fast register allocator"),
65+
clEnumValN(RegAllocType::Basic, "basic", "Basic register allocator"),
66+
clEnumValN(RegAllocType::Greedy, "greedy",
67+
"Greedy register allocator")));
5568

5669
static cl::opt<bool>
5770
DebugPM("debug-pass-manager", cl::Hidden,

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