Changed the patch to use CodeGenOpts instead of target features.

I simplified the clang test significantly.
I also completely removed the llc test. Since the code gen opt is now internal
there is no good way that I know of to test it using llc.

Author: stefanp-synopsys

clang/include/clang/Basic/CodeGenOptions.def

@@ -197,6 +197,7 @@ CODEGENOPT(HIPCorrectlyRoundedDivSqrt, 1, 1) ///< -fno-hip-fp32-correctly-rounde
 CODEGENOPT(HIPSaveKernelArgName, 1, 0) ///< Set when -fhip-kernel-arg-name is enabled.
 CODEGENOPT(UniqueInternalLinkageNames, 1, 0) ///< Internal Linkage symbols get unique names.
 CODEGENOPT(SplitMachineFunctions, 1, 0) ///< Split machine functions using profile information.
+CODEGENOPT(UseFullRegisterNames, 1, 0) ///< Print full register names in assembly -mregnames
 
 /// When false, this attempts to generate code as if the result of an
 /// overflowing conversion matches the overflowing behavior of a target's native

clang/include/clang/Driver/Options.td

@@ -4789,10 +4789,12 @@ def mrop_protect : Flag<["-"], "mrop-protect">,
     Group<m_ppc_Features_Group>;
 def mprivileged : Flag<["-"], "mprivileged">,
     Group<m_ppc_Features_Group>;
-def mregnames : Flag<["-"], "mregnames">, Group<m_ppc_Features_Group>,
-                Visibility<[ClangOption]>;
-def mno_regnames : Flag<["-"], "mno-regnames">, Group<m_ppc_Features_Group>,
-                   Visibility<[ClangOption]>;
+
+defm regnames : BoolOption<"m", "regnames",
+  CodeGenOpts<"UseFullRegisterNames">, DefaultFalse,
+  PosFlag<SetTrue, [], [ClangOption, CC1Option], "Use full register names when writing assembly output">,
+  NegFlag<SetFalse, [], [ClangOption], "Use only register numbers when writing assembly output">>,
+  Group<m_Group>;
 } // let Flags = [TargetSpecific]
 def maix_small_local_exec_tls : Flag<["-"], "maix-small-local-exec-tls">,
   Group<m_ppc_Features_Group>,

clang/lib/Basic/Targets/PPC.cpp

@@ -89,8 +89,6 @@ bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
       IsISA3_1 = true;
     } else if (Feature == "+quadword-atomics") {
       HasQuadwordAtomics = true;
-    } else if (Feature == "+regnames") {
-      FullRegisterNames = true;
     }
     // TODO: Finish this list and add an assert that we've handled them
     // all.
@@ -553,9 +551,6 @@ bool PPCTargetInfo::initFeatureMap(
   // off by default.
   Features["aix-small-local-exec-tls"] = false;
 
-  // By default full register names are not used in assembly.
-  Features["regnames"] = false;
-
   Features["spe"] = llvm::StringSwitch<bool>(CPU)
                         .Case("8548", true)
                         .Case("e500", true)
@@ -705,7 +700,6 @@ bool PPCTargetInfo::hasFeature(StringRef Feature) const {
       .Case("isa-v30-instructions", IsISA3_0)
       .Case("isa-v31-instructions", IsISA3_1)
       .Case("quadword-atomics", HasQuadwordAtomics)
-      .Case("regnames", FullRegisterNames)
       .Default(false);
 }
 

clang/lib/Basic/Targets/PPC.h

@@ -80,7 +80,6 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo {
   bool IsISA3_0 = false;
   bool IsISA3_1 = false;
   bool HasQuadwordAtomics = false;
-  bool FullRegisterNames = false;
 
 protected:
   std::string ABI;

clang/lib/CodeGen/BackendUtil.cpp

@@ -488,6 +488,7 @@ static bool initTargetOptions(DiagnosticsEngine &Diags,
   Options.MCOptions.Argv0 = CodeGenOpts.Argv0;
   Options.MCOptions.CommandLineArgs = CodeGenOpts.CommandLineArgs;
   Options.MCOptions.AsSecureLogFile = CodeGenOpts.AsSecureLogFile;
+  Options.MCOptions.UseFullRegisterNames = CodeGenOpts.UseFullRegisterNames;
   Options.MisExpect = CodeGenOpts.MisExpect;
 
   return true;

clang/lib/Driver/ToolChains/Clang.cpp

@@ -5014,6 +5014,12 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA,
     Args.AddLastArg(CmdArgs, options::OPT_fthinlto_index_EQ);
   }
 
+  if (const Arg *A = Args.getLastArg(options::OPT_mregnames,
+                                     options::OPT_mno_regnames)) {
+    if (A->getOption().matches(options::OPT_mregnames))
+      Args.AddLastArg(CmdArgs, options::OPT_mregnames);
+  }
+
   if (Args.getLastArg(options::OPT_fthin_link_bitcode_EQ))
     Args.AddLastArg(CmdArgs, options::OPT_fthin_link_bitcode_EQ);
 

clang/lib/Frontend/CompilerInvocation.cpp

@@ -1780,6 +1780,9 @@ bool CompilerInvocation::ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args,
       Opts.setDebugInfo(llvm::codegenoptions::LimitedDebugInfo);
   }
 
+  if (const Arg *A = Args.getLastArg(OPT_mregnames))
+    Opts.UseFullRegisterNames = true;
+
   for (const auto &Arg : Args.getAllArgValues(OPT_fdebug_prefix_map_EQ)) {
     auto Split = StringRef(Arg).split('=');
     Opts.DebugPrefixMap.emplace_back(Split.first, Split.second);

clang/test/CodeGen/PowerPC/ppc-full-reg-names.c

@@ -1,78 +1,20 @@
 // REQUIRES: powerpc-registered-target
-// RUN: %clang -target powerpc-ibm-aix-xcoff -mcpu=pwr8 -O3 -S -emit-llvm -mregnames \
+// RUN: %clang -### -target powerpc-ibm-aix-xcoff -mcpu=pwr8 -O3 -mregnames \
 // RUN:   -maltivec %s -o - | FileCheck %s --check-prefix=FULLNAMES
-// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -O3 -S -emit-llvm -mregnames \
+// RUN: %clang -### -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -O3 -mregnames \
 // RUN:   -maltivec %s -o - | FileCheck %s --check-prefix=FULLNAMES
-// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -O3 -S -emit-llvm -mregnames \
+// RUN: %clang -### -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -O3 -mregnames \
 // RUN:   -maltivec %s -o - | FileCheck %s --check-prefix=FULLNAMES
-// RUN: %clang -target powerpc-ibm-aix-xcoff -mcpu=pwr8 -O3 -S -emit-llvm -mno-regnames \
+// RUN: %clang -### -target powerpc-ibm-aix-xcoff -mcpu=pwr8 -O3 -mno-regnames \
 // RUN:   -maltivec %s -o - | FileCheck %s --check-prefix=NOFULLNAMES
-// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -O3 -S -emit-llvm -mno-regnames \
+// RUN: %clang -### -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -O3 -mno-regnames \
 // RUN:   -maltivec %s -o - | FileCheck %s --check-prefix=NOFULLNAMES
-// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -O3 -S -emit-llvm -mno-regnames \
+// RUN: %clang -### -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -O3 -mno-regnames \
 // RUN:   -maltivec %s -o - | FileCheck %s --check-prefix=NOFULLNAMES
 
-// Also check the assembly to make sure that the full names are used.
-// RUN: %clang -target powerpc-ibm-aix-xcoff -mcpu=pwr8 -O3 -S -mregnames \
-// RUN:   -maltivec %s -o - | FileCheck %s --check-prefix=ASMFULLNAMES
-// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -O3 -S -mregnames \
-// RUN:   -maltivec %s -o - | FileCheck %s --check-prefix=ASMFULLNAMES
-// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -O3 -S -mregnames \
-// RUN:   -maltivec %s -o - | FileCheck %s --check-prefix=ASMFULLNAMES
-// RUN: %clang -target powerpc-ibm-aix-xcoff -mcpu=pwr8 -O3 -S -mno-regnames \
-// RUN:   -maltivec %s -o - | FileCheck %s --check-prefix=ASMNOFULLNAMES
-// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -O3 -S -mno-regnames \
-// RUN:   -maltivec %s -o - | FileCheck %s --check-prefix=ASMNOFULLNAMES
-// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -O3 -S -mno-regnames \
-// RUN:   -maltivec %s -o - | FileCheck %s --check-prefix=ASMNOFULLNAMES
-
-
-
-// FULLNAMES-LABEL: @IntNames
-// FULLNAMES-SAME:  #0
-// NOFULLNAMES-LABEL: @IntNames
-// NOFULLNAMES-SAME:  #0
-// ASMFULLNAMES-LABEL: IntNames:
-// ASMFULLNAMES:         add r3, r4, r3
-// ASMFULLNAMES:         blr
-// ASMNOFULLNAMES-LABEL: IntNames:
-// ASMNOFULLNAMES:         add 3, 4, 3
-// ASMNOFULLNAMES:         blr
-int IntNames(int a, int b) {
-  return a + b;
-}
-
-// FULLNAMES-LABEL: @FPNames
-// FULLNAMES-SAME:  #0
-// NOFULLNAMES-LABEL: @FPNames
-// NOFULLNAMES-SAME:  #0
-// ASMFULLNAMES-LABEL: FPNames:
-// ASMFULLNAMES:         xsadddp f1, f1, f2
-// ASMFULLNAMES:         blr
-// ASMNOFULLNAMES-LABEL: FPNames:
-// ASMNOFULLNAMES:         xsadddp 1, 1, 2
-// ASMNOFULLNAMES:         blr
-double FPNames(double a, double b) {
-  return a + b;
-}
-
-// FULLNAMES-LABEL: @VecNames
-// FULLNAMES-SAME:  #0
-// NOFULLNAMES-LABEL: @VecNames
-// NOFULLNAMES-SAME:  #0
-// ASMFULLNAMES-LABEL: VecNames:
-// ASMFULLNAMES:         xvaddsp vs34, vs34, vs35
-// ASMFULLNAMES:         blr
-// ASMNOFULLNAMES-LABEL: VecNames:
-// ASMNOFULLNAMES:         xvaddsp 34, 34, 35
-// ASMNOFULLNAMES:         blr
-vector float VecNames(vector float a, vector float b) {
-  return a + b;
-}
-
-// FULLNAMES: attributes #0 = {
-// FULLNAMES-SAME: +regnames
-// NOFULLNAMES: attributes #0 = {
-// NOFULLNAMES-SAME: -regnames
+// FULLNAMES: clang
+// FULLNAMES-SAME: -mregnames
+// NOFULLNAMES: clang
+// NOFULLNAMES-SAME-NOT: -mregnames
 
 

llvm/include/llvm/MC/MCAsmInfo.h

@@ -240,6 +240,9 @@ class MCAsmInfo {
   /// True if the target supports LEB128 directives.
   bool HasLEB128Directives = true;
 
+  /// True if full register names are printed.
+  bool UseFullRegisterNames = false;
+
   //===--- Data Emission Directives -------------------------------------===//
 
   /// This should be set to the directive used to get some number of zero (and
@@ -710,6 +713,9 @@ class MCAsmInfo {
 
   bool hasLEB128Directives() const { return HasLEB128Directives; }
 
+  bool useFullRegisterNames() const { return UseFullRegisterNames; }
+  void setFullRegisterNames(bool V) { UseFullRegisterNames = V; }
+
   const char *getZeroDirective() const { return ZeroDirective; }
   bool doesZeroDirectiveSupportNonZeroValue() const {
     return ZeroDirectiveSupportsNonZeroValue;

llvm/include/llvm/MC/MCTargetOptions.h

@@ -89,6 +89,9 @@ class MCTargetOptions {
   // functions on Darwins.
   bool EmitCompactUnwindNonCanonical : 1;
 
+  // Whether or not to use full register names on PowerPC.
+  bool UseFullRegisterNames : 1;
+
   MCTargetOptions();
 
   /// getABIName - If this returns a non-empty string this represents the

llvm/lib/CodeGen/LLVMTargetMachine.cpp

@@ -81,6 +81,8 @@ void LLVMTargetMachine::initAsmInfo() {
 
   TmpAsmInfo->setRelaxELFRelocations(Options.RelaxELFRelocations);
 
+  TmpAsmInfo->setFullRegisterNames(Options.MCOptions.UseFullRegisterNames);
+
   if (Options.ExceptionModel != ExceptionHandling::None)
     TmpAsmInfo->setExceptionsType(Options.ExceptionModel);
 

llvm/lib/MC/MCAsmInfo.cpp

@@ -67,6 +67,7 @@ MCAsmInfo::MCAsmInfo() {
   UseIntegratedAssembler = true;
   ParseInlineAsmUsingAsmParser = false;
   PreserveAsmComments = true;
+  UseFullRegisterNames = false;
 }
 
 MCAsmInfo::~MCAsmInfo() = default;

llvm/lib/MC/MCTargetOptions.cpp

@@ -19,7 +19,7 @@ MCTargetOptions::MCTargetOptions()
       PreserveAsmComments(true), Dwarf64(false),
       EmitDwarfUnwind(EmitDwarfUnwindType::Default),
       MCUseDwarfDirectory(DefaultDwarfDirectory),
-      EmitCompactUnwindNonCanonical(false) {}
+      EmitCompactUnwindNonCanonical(false), UseFullRegisterNames(false) {}
 
 StringRef MCTargetOptions::getABIName() const {
   return ABIName;

llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp

@@ -13,6 +13,7 @@
 #include "MCTargetDesc/PPCInstPrinter.h"
 #include "MCTargetDesc/PPCMCTargetDesc.h"
 #include "MCTargetDesc/PPCPredicates.h"
+#include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstrInfo.h"
@@ -614,8 +615,8 @@ bool PPCInstPrinter::showRegistersWithPercentPrefix(const char *RegName) const {
 /// getVerboseConditionalRegName - This method expands the condition register
 /// when requested explicitly or targetting Darwin.
 const char *PPCInstPrinter::getVerboseConditionRegName(
-    unsigned RegNum, unsigned RegEncoding, const MCSubtargetInfo &STI) const {
-  if (!FullRegNames && !STI.hasFeature(PPC::FeatureFullRegisterNames))
+    unsigned RegNum, unsigned RegEncoding) const {
+  if (!FullRegNames && !MAI.useFullRegisterNames())
     return nullptr;
   if (RegNum < PPC::CR0EQ || RegNum > PPC::CR7UN)
     return nullptr;
@@ -634,9 +635,9 @@ const char *PPCInstPrinter::getVerboseConditionRegName(
 
 // showRegistersWithPrefix - This method determines whether registers
 // should be number-only or include the prefix.
-bool PPCInstPrinter::showRegistersWithPrefix(const MCSubtargetInfo &STI) const {
+bool PPCInstPrinter::showRegistersWithPrefix() const {
   return FullRegNamesWithPercent || FullRegNames ||
-         STI.hasFeature(PPC::FeatureFullRegisterNames);
+         MAI.useFullRegisterNames();
 }
 
 void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
@@ -648,12 +649,12 @@ void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
       Reg = PPC::getRegNumForOperand(MII.get(MI->getOpcode()), Reg, OpNo);
 
     const char *RegName;
-    RegName = getVerboseConditionRegName(Reg, MRI.getEncodingValue(Reg), STI);
+    RegName = getVerboseConditionRegName(Reg, MRI.getEncodingValue(Reg));
     if (RegName == nullptr)
      RegName = getRegisterName(Reg);
     if (showRegistersWithPercentPrefix(RegName))
       O << "%";
-    if (!showRegistersWithPrefix(STI))
+    if (!showRegistersWithPrefix())
       RegName = PPC::stripRegisterPrefix(RegName);
 
     O << RegName;

llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h

@@ -22,9 +22,9 @@ class PPCInstPrinter : public MCInstPrinter {
   Triple TT;
 private:
   bool showRegistersWithPercentPrefix(const char *RegName) const;
-  bool showRegistersWithPrefix(const MCSubtargetInfo &STI) const;
-  const char *getVerboseConditionRegName(unsigned RegNum, unsigned RegEncoding,
-                                         const MCSubtargetInfo &STI) const;
+  bool showRegistersWithPrefix() const;
+  const char *getVerboseConditionRegName(unsigned RegNum,
+                                         unsigned RegEncoding) const;
 
 public:
   PPCInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,

llvm/lib/Target/PowerPC/PPC.td

@@ -338,10 +338,6 @@ def FeaturePredictableSelectIsExpensive :
 def FeatureFastMFLR : SubtargetFeature<"fast-MFLR", "HasFastMFLR", "true",
                                        "MFLR is a fast instruction">;
 
-def FeatureFullRegisterNames :
-  SubtargetFeature<"regnames", "FullRegisterNames", "true",
-                   "Use full register names in assembly.">;
-
 // Since new processors generally contain a superset of features of those that
 // came before them, the idea is to make implementations of new processors
 // less error prone and easier to read.