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[X86][NFC] Simplify the definitions of shift instructions
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‎llvm/lib/Target/X86/X86InstrShiftRotate.td

Lines changed: 82 additions & 274 deletions
Original file line numberDiff line numberDiff line change
@@ -10,295 +10,103 @@
1010
//
1111
//===----------------------------------------------------------------------===//
1212

13-
// FIXME: Someone needs to smear multipattern goodness all over this file.
14-
15-
let Defs = [EFLAGS], hasSideEffects = 0 in {
16-
17-
let Constraints = "$src1 = $dst" in {
18-
let Uses = [CL], SchedRW = [WriteShiftCL] in {
19-
def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
20-
"shl{b}\t{%cl, $dst|$dst, cl}",
21-
[(set GR8:$dst, (shl GR8:$src1, CL))]>;
22-
def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
23-
"shl{w}\t{%cl, $dst|$dst, cl}",
24-
[(set GR16:$dst, (shl GR16:$src1, CL))]>, OpSize16;
25-
def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
26-
"shl{l}\t{%cl, $dst|$dst, cl}",
27-
[(set GR32:$dst, (shl GR32:$src1, CL))]>, OpSize32;
28-
def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
29-
"shl{q}\t{%cl, $dst|$dst, cl}",
30-
[(set GR64:$dst, (shl GR64:$src1, CL))]>;
31-
} // Uses = [CL], SchedRW
32-
33-
let SchedRW = [WriteShift] in {
34-
let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
35-
def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2),
36-
"shl{b}\t{$src2, $dst|$dst, $src2}",
37-
[(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
38-
39-
def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
40-
"shl{w}\t{$src2, $dst|$dst, $src2}",
41-
[(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>,
42-
OpSize16;
43-
def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
44-
"shl{l}\t{$src2, $dst|$dst, $src2}",
45-
[(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>,
46-
OpSize32;
47-
def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst),
48-
(ins GR64:$src1, u8imm:$src2),
49-
"shl{q}\t{$src2, $dst|$dst, $src2}",
50-
[(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
51-
} // isConvertibleToThreeAddress = 1
52-
53-
def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
54-
"shl{b}\t$dst", []>;
55-
def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
56-
"shl{w}\t$dst", []>, OpSize16;
57-
def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
58-
"shl{l}\t$dst", []>, OpSize32;
59-
def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
60-
"shl{q}\t$dst", []>;
61-
} // SchedRW
62-
} // Constraints = "$src = $dst"
63-
64-
// FIXME: Why do we need an explicit "Uses = [CL]" when the instr has a pattern
65-
// using CL?
66-
let Uses = [CL], SchedRW = [WriteShiftCLLd, WriteRMW] in {
67-
def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
68-
"shl{b}\t{%cl, $dst|$dst, cl}",
69-
[(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
70-
def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
71-
"shl{w}\t{%cl, $dst|$dst, cl}",
72-
[(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>,
73-
OpSize16;
74-
def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
75-
"shl{l}\t{%cl, $dst|$dst, cl}",
76-
[(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>,
77-
OpSize32;
78-
def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
79-
"shl{q}\t{%cl, $dst|$dst, cl}",
80-
[(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>,
81-
Requires<[In64BitMode]>;
82-
} // Uses, SchedRW
83-
84-
let SchedRW = [WriteShiftLd, WriteRMW], mayLoad = 1, mayStore = 1 in {
85-
def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, u8imm:$src),
86-
"shl{b}\t{$src, $dst|$dst, $src}",
87-
[(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
88-
def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, u8imm:$src),
89-
"shl{w}\t{$src, $dst|$dst, $src}",
90-
[(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
91-
OpSize16;
92-
def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, u8imm:$src),
93-
"shl{l}\t{$src, $dst|$dst, $src}",
94-
[(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
95-
OpSize32;
96-
def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, u8imm:$src),
97-
"shl{q}\t{$src, $dst|$dst, $src}",
98-
[(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
99-
Requires<[In64BitMode]>;
100-
101-
// Shift by 1
102-
def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
103-
"shl{b}\t$dst", []>;
104-
def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
105-
"shl{w}\t$dst", []>, OpSize16;
106-
def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
107-
"shl{l}\t$dst", []>, OpSize32;
108-
def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
109-
"shl{q}\t$dst", []>, Requires<[In64BitMode]>;
110-
} // SchedRW, mayLoad, mayStore
111-
112-
let Constraints = "$src1 = $dst" in {
113-
let Uses = [CL], SchedRW = [WriteShiftCL] in {
114-
def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1),
115-
"shr{b}\t{%cl, $dst|$dst, cl}",
116-
[(set GR8:$dst, (srl GR8:$src1, CL))]>;
117-
def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
118-
"shr{w}\t{%cl, $dst|$dst, cl}",
119-
[(set GR16:$dst, (srl GR16:$src1, CL))]>, OpSize16;
120-
def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
121-
"shr{l}\t{%cl, $dst|$dst, cl}",
122-
[(set GR32:$dst, (srl GR32:$src1, CL))]>, OpSize32;
123-
def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
124-
"shr{q}\t{%cl, $dst|$dst, cl}",
125-
[(set GR64:$dst, (srl GR64:$src1, CL))]>;
126-
} // Uses, SchedRW
13+
//===----------------------------------------------------------------------===//
14+
// Shift instructions
15+
//===----------------------------------------------------------------------===//
12716

128-
let SchedRW = [WriteShift] in {
129-
def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, u8imm:$src2),
130-
"shr{b}\t{$src2, $dst|$dst, $src2}",
131-
[(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
132-
def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
133-
"shr{w}\t{$src2, $dst|$dst, $src2}",
134-
[(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>,
135-
OpSize16;
136-
def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
137-
"shr{l}\t{$src2, $dst|$dst, $src2}",
138-
[(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>,
139-
OpSize32;
140-
def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, u8imm:$src2),
141-
"shr{q}\t{$src2, $dst|$dst, $src2}",
142-
[(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>;
143-
144-
// Shift right by 1
145-
def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
146-
"shr{b}\t$dst", []>;
147-
def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
148-
"shr{w}\t$dst", []>, OpSize16;
149-
def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
150-
"shr{l}\t$dst", []>, OpSize32;
151-
def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
152-
"shr{q}\t$dst", []>;
153-
} // SchedRW
154-
} // Constraints = "$src = $dst"
17+
class ShiftOpRCL_R<string m, Format f, X86TypeInfo t, SDPatternOperator node>
18+
: ITy<0xD3, f, t, (outs t.RegClass:$dst), (ins t.RegClass:$src1), m,
19+
"{%cl, $src1|$src1, cl}",
20+
[(set t.RegClass:$dst, (node t.RegClass:$src1, CL))]>,
21+
Sched<[WriteShiftCL]> {
22+
let Uses = [CL];
23+
}
15524

25+
class ShiftOpRI_R<string m, Format f, X86TypeInfo t, SDPatternOperator node>
26+
: ITy<0xC1, f, t, (outs t.RegClass:$dst), (ins t.RegClass:$src1, u8imm:$src2), m,
27+
binop_args,
28+
[(set t.RegClass:$dst, (node t.RegClass:$src1, (i8 imm:$src2)))]>,
29+
Sched<[WriteShift]> {
30+
let ImmT = Imm8;
31+
}
15632

157-
let Uses = [CL], SchedRW = [WriteShiftCLLd, WriteRMW] in {
158-
def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
159-
"shr{b}\t{%cl, $dst|$dst, cl}",
160-
[(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
161-
def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
162-
"shr{w}\t{%cl, $dst|$dst, cl}",
163-
[(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
164-
OpSize16;
165-
def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
166-
"shr{l}\t{%cl, $dst|$dst, cl}",
167-
[(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>,
168-
OpSize32;
169-
def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
170-
"shr{q}\t{%cl, $dst|$dst, cl}",
171-
[(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>,
172-
Requires<[In64BitMode]>;
173-
} // Uses, SchedRW
33+
class ShiftOpR1<string m, Format f, X86TypeInfo t>
34+
: ITy<0xD1, f, t, (outs t.RegClass:$dst), (ins t.RegClass:$src1), m,
35+
"$src1", []>, Sched<[WriteShift]>;
36+
37+
class ShiftOpMCL<string m, Format f, X86TypeInfo t, SDPatternOperator node>
38+
: ITy<0xD3, f, t, (outs), (ins t.MemOperand:$src1), m,
39+
"{%cl, $src1|$src1, cl}",
40+
[(store (node (t.LoadNode addr:$src1), CL), addr:$src1)]>,
41+
Sched<[WriteShiftCLLd, WriteRMW]> {
42+
let Uses = [CL];
43+
let mayLoad = 1;
44+
let mayStore = 1;
45+
}
17446

175-
let SchedRW = [WriteShiftLd, WriteRMW], mayLoad = 1, mayStore = 1 in {
176-
def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, u8imm:$src),
177-
"shr{b}\t{$src, $dst|$dst, $src}",
178-
[(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
179-
def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, u8imm:$src),
180-
"shr{w}\t{$src, $dst|$dst, $src}",
181-
[(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
182-
OpSize16;
183-
def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, u8imm:$src),
184-
"shr{l}\t{$src, $dst|$dst, $src}",
185-
[(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
186-
OpSize32;
187-
def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, u8imm:$src),
188-
"shr{q}\t{$src, $dst|$dst, $src}",
189-
[(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
190-
Requires<[In64BitMode]>;
191-
192-
// Shift by 1
193-
def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
194-
"shr{b}\t$dst", []>;
195-
def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
196-
"shr{w}\t$dst", []>, OpSize16;
197-
def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
198-
"shr{l}\t$dst", []>, OpSize32;
199-
def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
200-
"shr{q}\t$dst", []>, Requires<[In64BitMode]>;
201-
} // SchedRW, mayLoad, mayStore
47+
class ShiftOpMI<string m, Format f, X86TypeInfo t, SDPatternOperator node>
48+
: ITy<0xC1, f, t, (outs), (ins t.MemOperand:$src1, u8imm:$src2), m,
49+
binop_args, [(store (node (t.LoadNode addr:$src1), (i8 imm:$src2)), addr:$src1)]>,
50+
Sched<[WriteShiftLd, WriteRMW]> {
51+
let ImmT = Imm8;
52+
let mayLoad = 1;
53+
let mayStore = 1;
54+
}
20255

56+
class ShiftOpM1<string m, Format f, X86TypeInfo t>
57+
: ITy<0xD1, f, t, (outs), (ins t.MemOperand:$src1), m,
58+
"$src1", []>, Sched<[WriteShiftLd, WriteRMW]> {
59+
let mayLoad = 1;
60+
let mayStore = 1;
61+
}
20362

204-
let Constraints = "$src1 = $dst" in {
205-
let Uses = [CL], SchedRW = [WriteShiftCL] in {
206-
def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
207-
"sar{b}\t{%cl, $dst|$dst, cl}",
208-
[(set GR8:$dst, (sra GR8:$src1, CL))]>;
209-
def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
210-
"sar{w}\t{%cl, $dst|$dst, cl}",
211-
[(set GR16:$dst, (sra GR16:$src1, CL))]>,
212-
OpSize16;
213-
def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
214-
"sar{l}\t{%cl, $dst|$dst, cl}",
215-
[(set GR32:$dst, (sra GR32:$src1, CL))]>,
216-
OpSize32;
217-
def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
218-
"sar{q}\t{%cl, $dst|$dst, cl}",
219-
[(set GR64:$dst, (sra GR64:$src1, CL))]>;
220-
} // Uses, SchedRW
63+
multiclass Shift<string m, Format RegMRM, Format MemMRM, SDPatternOperator node,
64+
bit ConvertibleToThreeAddress> {
65+
let Constraints = "$src1 = $dst" in {
66+
def 8rCL : ShiftOpRCL_R<m, RegMRM, Xi8, node>, DefEFLAGS;
67+
def 16rCL : ShiftOpRCL_R<m, RegMRM, Xi16, node>, DefEFLAGS, OpSize16;
68+
def 32rCL : ShiftOpRCL_R<m, RegMRM, Xi32, node>, DefEFLAGS, OpSize32;
69+
def 64rCL : ShiftOpRCL_R<m, RegMRM, Xi64, node>, DefEFLAGS;
70+
71+
let isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
72+
def 8ri : ShiftOpRI_R<m, RegMRM, Xi8, node>, DefEFLAGS;
73+
def 16ri : ShiftOpRI_R<m, RegMRM, Xi16, node>, DefEFLAGS, OpSize16;
74+
def 32ri : ShiftOpRI_R<m, RegMRM, Xi32, node>, DefEFLAGS, OpSize32;
75+
def 64ri : ShiftOpRI_R<m, RegMRM, Xi64, node>, DefEFLAGS;
76+
}
77+
78+
def 8r1 : ShiftOpR1<m, RegMRM, Xi8>, DefEFLAGS;
79+
def 16r1 : ShiftOpR1<m, RegMRM, Xi16>, DefEFLAGS, OpSize16;
80+
def 32r1 : ShiftOpR1<m, RegMRM, Xi32>, DefEFLAGS, OpSize32;
81+
def 64r1 : ShiftOpR1<m, RegMRM, Xi64>, DefEFLAGS;
82+
}
22183

222-
let SchedRW = [WriteShift] in {
223-
def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2),
224-
"sar{b}\t{$src2, $dst|$dst, $src2}",
225-
[(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
226-
def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
227-
"sar{w}\t{$src2, $dst|$dst, $src2}",
228-
[(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
229-
OpSize16;
230-
def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
231-
"sar{l}\t{$src2, $dst|$dst, $src2}",
232-
[(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>,
233-
OpSize32;
234-
def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst),
235-
(ins GR64:$src1, u8imm:$src2),
236-
"sar{q}\t{$src2, $dst|$dst, $src2}",
237-
[(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>;
238-
239-
// Shift by 1
240-
def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
241-
"sar{b}\t$dst", []>;
242-
def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
243-
"sar{w}\t$dst", []>, OpSize16;
244-
def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
245-
"sar{l}\t$dst", []>, OpSize32;
246-
def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
247-
"sar{q}\t$dst", []>;
248-
} // SchedRW
249-
} // Constraints = "$src = $dst"
84+
def 8mCL : ShiftOpMCL<m, MemMRM, Xi8, node>, DefEFLAGS;
85+
def 16mCL : ShiftOpMCL<m, MemMRM, Xi16, node>, DefEFLAGS, OpSize16;
86+
def 32mCL : ShiftOpMCL<m, MemMRM, Xi32, node>, DefEFLAGS, OpSize32;
87+
def 64mCL : ShiftOpMCL<m, MemMRM, Xi64, node>, DefEFLAGS, Requires<[In64BitMode]>;
25088

89+
def 8mi : ShiftOpMI<m, MemMRM, Xi8, node>, DefEFLAGS;
90+
def 16mi : ShiftOpMI<m, MemMRM, Xi16, node>, DefEFLAGS, OpSize16;
91+
def 32mi : ShiftOpMI<m, MemMRM, Xi32, node>, DefEFLAGS, OpSize32;
92+
def 64mi : ShiftOpMI<m, MemMRM, Xi64, node>, DefEFLAGS, Requires<[In64BitMode]>;
25193

252-
let Uses = [CL], SchedRW = [WriteShiftCLLd, WriteRMW] in {
253-
def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
254-
"sar{b}\t{%cl, $dst|$dst, cl}",
255-
[(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
256-
def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
257-
"sar{w}\t{%cl, $dst|$dst, cl}",
258-
[(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>,
259-
OpSize16;
260-
def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
261-
"sar{l}\t{%cl, $dst|$dst, cl}",
262-
[(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>,
263-
OpSize32;
264-
def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
265-
"sar{q}\t{%cl, $dst|$dst, cl}",
266-
[(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>,
267-
Requires<[In64BitMode]>;
268-
} // Uses, SchedRW
94+
def 8m1 : ShiftOpM1<m, MemMRM, Xi8>, DefEFLAGS;
95+
def 16m1 : ShiftOpM1<m, MemMRM, Xi16>, DefEFLAGS, OpSize16;
96+
def 32m1 : ShiftOpM1<m, MemMRM, Xi32>, DefEFLAGS, OpSize32;
97+
def 64m1 : ShiftOpM1<m, MemMRM, Xi64>, DefEFLAGS, Requires<[In64BitMode]>;
98+
}
26999

270-
let SchedRW = [WriteShiftLd, WriteRMW], mayLoad = 1, mayStore = 1 in {
271-
def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, u8imm:$src),
272-
"sar{b}\t{$src, $dst|$dst, $src}",
273-
[(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
274-
def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, u8imm:$src),
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"sar{w}\t{$src, $dst|$dst, $src}",
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[(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
277-
OpSize16;
278-
def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, u8imm:$src),
279-
"sar{l}\t{$src, $dst|$dst, $src}",
280-
[(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
281-
OpSize32;
282-
def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, u8imm:$src),
283-
"sar{q}\t{$src, $dst|$dst, $src}",
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[(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
285-
Requires<[In64BitMode]>;
286-
287-
// Shift by 1
288-
def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
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"sar{b}\t$dst", []>;
290-
def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
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"sar{w}\t$dst", []>, OpSize16;
292-
def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
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"sar{l}\t$dst", []>, OpSize32;
294-
def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
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"sar{q}\t$dst", []>, Requires<[In64BitMode]>;
296-
} // SchedRW
100+
defm SHL: Shift<"shl", MRM4r, MRM4m, shl, 1>;
101+
defm SHR: Shift<"shr", MRM5r, MRM5m, srl, 0>;
102+
defm SAR: Shift<"sar", MRM7r, MRM7m, sra, 0>;
297103

298104
//===----------------------------------------------------------------------===//
299105
// Rotate instructions
300106
//===----------------------------------------------------------------------===//
301107

108+
let Defs = [EFLAGS], hasSideEffects = 0 in {
109+
302110
let Constraints = "$src1 = $dst" in {
303111

304112
let Uses = [CL, EFLAGS], SchedRW = [WriteRotateCL] in {

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