Revert "[CodeGen][ARM] Enable Swing Module Scheduling for ARM"

This reverts commit 28d09bb
while I investigate a buildbot failure.

Author: dpenry

llvm/include/llvm/CodeGen/MachinePipeliner.h

@@ -84,8 +84,6 @@ class MachinePipeliner : public MachineFunctionPass {
     SmallVector<MachineOperand, 4> BrCond;
     MachineInstr *LoopInductionVar = nullptr;
     MachineInstr *LoopCompare = nullptr;
-    std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo> LoopPipelinerInfo =
-        nullptr;
   };
   LoopInfo LI;
 
@@ -121,7 +119,6 @@ class SwingSchedulerDAG : public ScheduleDAGInstrs {
   LiveIntervals &LIS;
   const RegisterClassInfo &RegClassInfo;
   unsigned II_setByPragma = 0;
-  TargetInstrInfo::PipelinerLoopInfo *LoopPipelinerInfo = nullptr;
 
   /// A toplogical ordering of the SUnits, which is needed for changing
   /// dependences and iterating over the SUnits.
@@ -199,11 +196,9 @@ class SwingSchedulerDAG : public ScheduleDAGInstrs {
 
 public:
   SwingSchedulerDAG(MachinePipeliner &P, MachineLoop &L, LiveIntervals &lis,
-                    const RegisterClassInfo &rci, unsigned II,
-                    TargetInstrInfo::PipelinerLoopInfo *PLI)
+                    const RegisterClassInfo &rci, unsigned II)
       : ScheduleDAGInstrs(*P.MF, P.MLI, false), Pass(P), Loop(L), LIS(lis),
-        RegClassInfo(rci), II_setByPragma(II), LoopPipelinerInfo(PLI),
-        Topo(SUnits, &ExitSU) {
+        RegClassInfo(rci), II_setByPragma(II), Topo(SUnits, &ExitSU) {
     P.MF->getSubtarget().getSMSMutations(Mutations);
     if (SwpEnableCopyToPhi)
       Mutations.push_back(std::make_unique<CopyToPhiMutation>());
@@ -594,13 +589,6 @@ class SMSchedule {
     return ScheduledInstrs[cycle];
   }
 
-  SmallSet<SUnit *, 8>
-  computeUnpipelineableNodes(SwingSchedulerDAG *SSD,
-                             TargetInstrInfo::PipelinerLoopInfo *PLI);
-
-  bool
-  normalizeNonPipelinedInstructions(SwingSchedulerDAG *SSD,
-                                    TargetInstrInfo::PipelinerLoopInfo *PLI);
   bool isValidSchedule(SwingSchedulerDAG *SSD);
   void finalizeSchedule(SwingSchedulerDAG *SSD);
   void orderDependence(SwingSchedulerDAG *SSD, SUnit *SU,

llvm/include/llvm/CodeGen/ModuloSchedule.h

@@ -191,8 +191,8 @@ class ModuloScheduleExpander {
   void generateProlog(unsigned LastStage, MachineBasicBlock *KernelBB,
                       ValueMapTy *VRMap, MBBVectorTy &PrologBBs);
   void generateEpilog(unsigned LastStage, MachineBasicBlock *KernelBB,
-                      MachineBasicBlock *OrigBB, ValueMapTy *VRMap,
-                      MBBVectorTy &EpilogBBs, MBBVectorTy &PrologBBs);
+                      ValueMapTy *VRMap, MBBVectorTy &EpilogBBs,
+                      MBBVectorTy &PrologBBs);
   void generateExistingPhis(MachineBasicBlock *NewBB, MachineBasicBlock *BB1,
                             MachineBasicBlock *BB2, MachineBasicBlock *KernelBB,
                             ValueMapTy *VRMap, InstrMapTy &InstrMap,

llvm/lib/CodeGen/MachinePipeliner.cpp

@@ -255,15 +255,13 @@ bool MachinePipeliner::scheduleLoop(MachineLoop &L) {
              << "Failed to pipeline loop";
     });
 
-    LI.LoopPipelinerInfo.reset();
     return Changed;
   }
 
   ++NumTrytoPipeline;
 
   Changed = swingModuloScheduler(L);
 
-  LI.LoopPipelinerInfo.reset();
   return Changed;
 }
 
@@ -356,8 +354,7 @@ bool MachinePipeliner::canPipelineLoop(MachineLoop &L) {
 
   LI.LoopInductionVar = nullptr;
   LI.LoopCompare = nullptr;
-  LI.LoopPipelinerInfo = TII->analyzeLoopForPipelining(L.getTopBlock());
-  if (!LI.LoopPipelinerInfo) {
+  if (!TII->analyzeLoopForPipelining(L.getTopBlock())) {
     LLVM_DEBUG(dbgs() << "Unable to analyzeLoop, can NOT pipeline Loop\n");
     NumFailLoop++;
     ORE->emit([&]() {
@@ -422,7 +419,7 @@ bool MachinePipeliner::swingModuloScheduler(MachineLoop &L) {
   assert(L.getBlocks().size() == 1 && "SMS works on single blocks only.");
 
   SwingSchedulerDAG SMS(*this, L, getAnalysis<LiveIntervals>(), RegClassInfo,
-                        II_setByPragma, LI.LoopPipelinerInfo.get());
+                        II_setByPragma);
 
   MachineBasicBlock *MBB = L.getHeader();
   // The kernel should not include any terminator instructions.  These
@@ -1425,7 +1422,7 @@ void SwingSchedulerDAG::CopyToPhiMutation::apply(ScheduleDAGInstrs *DAG) {
 /// We ignore the back-edge recurrence in order to avoid unbounded recursion
 /// in the calculation of the ASAP, ALAP, etc functions.
 static bool ignoreDependence(const SDep &D, bool isPred) {
-  if (D.isArtificial() || D.getSUnit()->isBoundaryNode())
+  if (D.isArtificial())
     return true;
   return D.getKind() == SDep::Anti && isPred;
 }
@@ -1474,8 +1471,6 @@ void SwingSchedulerDAG::computeNodeFunctions(NodeSetType &NodeSets) {
     SUnit *SU = &SUnits[I];
     for (const SDep &S : SU->Succs) {
       SUnit *succ = S.getSUnit();
-      if (succ->isBoundaryNode())
-        continue;
       if (S.getLatency() == 0)
         zeroLatencyHeight =
             std::max(zeroLatencyHeight, getZeroLatencyHeight(succ) + 1);
@@ -1793,8 +1788,7 @@ void SwingSchedulerDAG::addConnectedNodes(SUnit *SU, NodeSet &NewSet,
   NodesAdded.insert(SU);
   for (auto &SI : SU->Succs) {
     SUnit *Successor = SI.getSUnit();
-    if (!SI.isArtificial() && !Successor->isBoundaryNode() &&
-        NodesAdded.count(Successor) == 0)
+    if (!SI.isArtificial() && NodesAdded.count(Successor) == 0)
       addConnectedNodes(Successor, NewSet, NodesAdded);
   }
   for (auto &PI : SU->Preds) {
@@ -2086,11 +2080,6 @@ bool SwingSchedulerDAG::schedulePipeline(SMSchedule &Schedule) {
       });
     } while (++NI != NE && scheduleFound);
 
-    // If a schedule is found, ensure non-pipelined instructions are in stage 0
-    if (scheduleFound)
-      scheduleFound =
-          Schedule.normalizeNonPipelinedInstructions(this, LoopPipelinerInfo);
-
     // If a schedule is found, check if it is a valid schedule too.
     if (scheduleFound)
       scheduleFound = Schedule.isValidSchedule(this);
@@ -2274,7 +2263,7 @@ MachineInstr *SwingSchedulerDAG::findDefInLoop(Register Reg) {
 bool SwingSchedulerDAG::isLoopCarriedDep(SUnit *Source, const SDep &Dep,
                                          bool isSucc) {
   if ((Dep.getKind() != SDep::Order && Dep.getKind() != SDep::Output) ||
-      Dep.isArtificial() || Dep.getSUnit()->isBoundaryNode())
+      Dep.isArtificial())
     return false;
 
   if (!SwpPruneLoopCarried)
@@ -2441,7 +2430,7 @@ int SMSchedule::latestCycleInChain(const SDep &Dep) {
   while (!Worklist.empty()) {
     const SDep &Cur = Worklist.pop_back_val();
     SUnit *SuccSU = Cur.getSUnit();
-    if (Visited.count(SuccSU) || SuccSU->isBoundaryNode())
+    if (Visited.count(SuccSU))
       continue;
     std::map<SUnit *, int>::const_iterator it = InstrToCycle.find(SuccSU);
     if (it == InstrToCycle.end())
@@ -2708,91 +2697,21 @@ bool SMSchedule::isLoopCarriedDefOfUse(SwingSchedulerDAG *SSD,
   return false;
 }
 
-/// Determine transitive dependences of unpipelineable instructions
-SmallSet<SUnit *, 8> SMSchedule::computeUnpipelineableNodes(
-    SwingSchedulerDAG *SSD, TargetInstrInfo::PipelinerLoopInfo *PLI) {
-  SmallSet<SUnit *, 8> DoNotPipeline;
-  SmallVector<SUnit *, 8> Worklist;
-
-  for (auto &SU : SSD->SUnits)
-    if (SU.isInstr() && PLI->shouldIgnoreForPipelining(SU.getInstr()))
-      Worklist.push_back(&SU);
-
-  while (!Worklist.empty()) {
-    auto SU = Worklist.pop_back_val();
-    if (DoNotPipeline.count(SU))
-      continue;
-    LLVM_DEBUG(dbgs() << "Do not pipeline SU(" << SU->NodeNum << ")\n");
-    DoNotPipeline.insert(SU);
-    for (auto &Dep : SU->Preds)
-      Worklist.push_back(Dep.getSUnit());
-    if (SU->getInstr()->isPHI())
-      for (auto &Dep : SU->Succs)
-        if (Dep.getKind() == SDep::Anti)
-          Worklist.push_back(Dep.getSUnit());
-  }
-  return DoNotPipeline;
-}
-
-// Determine all instructions upon which any unpipelineable instruction depends
-// and ensure that they are in stage 0.  If unable to do so, return false.
-bool SMSchedule::normalizeNonPipelinedInstructions(
-    SwingSchedulerDAG *SSD, TargetInstrInfo::PipelinerLoopInfo *PLI) {
-  SmallSet<SUnit *, 8> DNP = computeUnpipelineableNodes(SSD, PLI);
-
-  int NewLastCycle = INT_MIN;
-  for (SUnit &SU : SSD->SUnits) {
-    if (!SU.isInstr())
-      continue;
-    if (!DNP.contains(&SU) || stageScheduled(&SU) == 0) {
-      NewLastCycle = std::max(NewLastCycle, InstrToCycle[&SU]);
-      continue;
-    }
-
-    // Put the non-pipelined instruction as early as possible in the schedule
-    int NewCycle = getFirstCycle();
-    for (auto &Dep : SU.Preds)
-      NewCycle = std::max(InstrToCycle[Dep.getSUnit()], NewCycle);
-
-    int OldCycle = InstrToCycle[&SU];
-    if (OldCycle != NewCycle) {
-      InstrToCycle[&SU] = NewCycle;
-      auto &OldS = getInstructions(OldCycle);
-      OldS.erase(std::remove(OldS.begin(), OldS.end(), &SU), OldS.end());
-      getInstructions(NewCycle).emplace_back(&SU);
-      LLVM_DEBUG(dbgs() << "SU(" << SU.NodeNum
-                        << ") is not pipelined; moving from cycle " << OldCycle
-                        << " to " << NewCycle << " Instr:" << *SU.getInstr());
-    }
-    NewLastCycle = std::max(NewLastCycle, NewCycle);
-  }
-  LastCycle = NewLastCycle;
-  return true;
-}
-
 // Check if the generated schedule is valid. This function checks if
 // an instruction that uses a physical register is scheduled in a
 // different stage than the definition. The pipeliner does not handle
 // physical register values that may cross a basic block boundary.
-// Furthermore, if a physical def/use pair is assigned to the same
-// cycle, orderDependence does not guarantee def/use ordering, so that
-// case should be considered invalid.  (The test checks for both
-// earlier and same-cycle use to be more robust.)
 bool SMSchedule::isValidSchedule(SwingSchedulerDAG *SSD) {
   for (SUnit &SU : SSD->SUnits) {
     if (!SU.hasPhysRegDefs)
       continue;
     int StageDef = stageScheduled(&SU);
-    int CycleDef = InstrToCycle[&SU];
     assert(StageDef != -1 && "Instruction should have been scheduled.");
     for (auto &SI : SU.Succs)
-      if (SI.isAssignedRegDep() && !SI.getSUnit()->isBoundaryNode())
-        if (Register::isPhysicalRegister(SI.getReg())) {
+      if (SI.isAssignedRegDep())
+        if (Register::isPhysicalRegister(SI.getReg()))
           if (stageScheduled(SI.getSUnit()) != StageDef)
             return false;
-          if (InstrToCycle[SI.getSUnit()] <= CycleDef)
-            return false;
-        }
   }
   return true;
 }

llvm/lib/CodeGen/ModuloSchedule.cpp

@@ -158,7 +158,7 @@ void ModuloScheduleExpander::generatePipelinedLoop() {
 
   SmallVector<MachineBasicBlock *, 4> EpilogBBs;
   // Generate the epilog instructions to complete the pipeline.
-  generateEpilog(MaxStageCount, KernelBB, BB, VRMap, EpilogBBs, PrologBBs);
+  generateEpilog(MaxStageCount, KernelBB, VRMap, EpilogBBs, PrologBBs);
 
   // We need this step because the register allocation doesn't handle some
   // situations well, so we insert copies to help out.
@@ -240,9 +240,11 @@ void ModuloScheduleExpander::generateProlog(unsigned LastStage,
 /// Generate the pipeline epilog code. The epilog code finishes the iterations
 /// that were started in either the prolog or the kernel.  We create a basic
 /// block for each stage that needs to complete.
-void ModuloScheduleExpander::generateEpilog(
-    unsigned LastStage, MachineBasicBlock *KernelBB, MachineBasicBlock *OrigBB,
-    ValueMapTy *VRMap, MBBVectorTy &EpilogBBs, MBBVectorTy &PrologBBs) {
+void ModuloScheduleExpander::generateEpilog(unsigned LastStage,
+                                            MachineBasicBlock *KernelBB,
+                                            ValueMapTy *VRMap,
+                                            MBBVectorTy &EpilogBBs,
+                                            MBBVectorTy &PrologBBs) {
   // We need to change the branch from the kernel to the first epilog block, so
   // this call to analyze branch uses the kernel rather than the original BB.
   MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
@@ -312,12 +314,7 @@ void ModuloScheduleExpander::generateEpilog(
   // Create a branch to the new epilog from the kernel.
   // Remove the original branch and add a new branch to the epilog.
   TII->removeBranch(*KernelBB);
-  assert((OrigBB == TBB || OrigBB == FBB) &&
-         "Unable to determine looping branch direction");
-  if (OrigBB != TBB)
-    TII->insertBranch(*KernelBB, EpilogStart, KernelBB, Cond, DebugLoc());
-  else
-    TII->insertBranch(*KernelBB, KernelBB, EpilogStart, Cond, DebugLoc());
+  TII->insertBranch(*KernelBB, KernelBB, EpilogStart, Cond, DebugLoc());
   // Add a branch to the loop exit.
   if (EpilogBBs.size() > 0) {
     MachineBasicBlock *LastEpilogBB = EpilogBBs.back();

llvm/lib/Target/ARM/ARM.td

@@ -494,10 +494,6 @@ def FeatureNoNegativeImmediates
 def FeatureUseMISched: SubtargetFeature<"use-misched", "UseMISched", "true",
                                         "Use the MachineScheduler">;
 
-// Use the MachinePipeliner for instruction scheduling for the subtarget.
-def FeatureUseMIPipeliner: SubtargetFeature<"use-mipipeliner", "UseMIPipeliner", "true",
-                                            "Use the MachinePipeliner">;
-
 // False if scheduling should happen again after register allocation.
 def FeatureNoPostRASched : SubtargetFeature<"disable-postra-scheduler",
     "DisablePostRAScheduler", "true",
@@ -1399,7 +1395,6 @@ def : ProcessorModel<"cortex-m4", CortexM4Model,        [ARMv7em,
 def : ProcessorModel<"cortex-m7", CortexM7Model,        [ARMv7em,
                                                          ProcM7,
                                                          FeatureFPARMv8_D16,
-                                                         FeatureUseMIPipeliner,
                                                          FeatureUseMISched]>;
 
 def : ProcNoItin<"cortex-m23",                          [ARMv8mBaseline,

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

@@ -6721,78 +6721,3 @@ unsigned llvm::getBLXpredOpcode(const MachineFunction &MF) {
   return (MF.getSubtarget<ARMSubtarget>().hardenSlsBlr()) ? ARM::BLX_pred_noip
                                                           : ARM::BLX_pred;
 }
-
-namespace {
-class ARMPipelinerLoopInfo : public TargetInstrInfo::PipelinerLoopInfo {
-  MachineInstr *Loop, *EndLoop, *LoopCount;
-  MachineFunction *MF;
-  const TargetInstrInfo *TII;
-
-  // Meanings of the various stuff with loop types:
-  // t2Bcc:
-  //   Loop = null -- there is no setup.
-  //   EndLoop = branch at end of original BB that will become a kernel
-  //   LoopCount = CC setter live into branch
-public:
-  ARMPipelinerLoopInfo(MachineInstr *Loop, MachineInstr *EndLoop,
-                       MachineInstr *LoopCount)
-      : Loop(Loop), EndLoop(EndLoop), LoopCount(LoopCount),
-        MF(EndLoop->getParent()->getParent()),
-        TII(MF->getSubtarget().getInstrInfo()) {}
-
-  bool shouldIgnoreForPipelining(const MachineInstr *MI) const override {
-    // Only ignore the terminator.
-    return MI == EndLoop || MI == LoopCount;
-  }
-
-  Optional<bool> createTripCountGreaterCondition(
-      int TC, MachineBasicBlock &MBB,
-      SmallVectorImpl<MachineOperand> &Cond) override {
-
-    if (isCondBranchOpcode(EndLoop->getOpcode())) {
-      Cond.push_back(EndLoop->getOperand(1));
-      Cond.push_back(EndLoop->getOperand(2));
-      if (EndLoop->getOperand(0).getMBB() == EndLoop->getParent()) {
-        TII->reverseBranchCondition(Cond);
-      }
-      return {};
-    } else
-      llvm_unreachable("Unknown EndLoop");
-  }
-
-  void setPreheader(MachineBasicBlock *NewPreheader) override {}
-
-  void adjustTripCount(int TripCountAdjust) override {}
-
-  void disposed() override {}
-};
-} // namespace
-
-std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
-ARMBaseInstrInfo::analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const {
-  MachineBasicBlock::iterator I = LoopBB->getFirstTerminator();
-  MachineBasicBlock *Preheader = *LoopBB->pred_begin();
-  if (Preheader == LoopBB)
-    Preheader = *std::next(LoopBB->pred_begin());
-
-  if (I != LoopBB->end() && I->getOpcode() == ARM::t2Bcc) {
-    // If the branch is a Bcc, then the CPSR should be set somewhere within the
-    // block.  We need to determine the reaching definition of CPSR so that
-    // it can be marked as non-pipelineable, allowing the pipeliner to force
-    // it into stage 0 or give up if it cannot or will not do so.
-    MachineInstr *CCSetter = nullptr;
-    for (auto &L : LoopBB->instrs()) {
-      if (L.isCall())
-        return nullptr;
-      if (isCPSRDefined(L))
-        CCSetter = &L;
-    }
-    if (CCSetter)
-      return std::make_unique<ARMPipelinerLoopInfo>(nullptr, &*I, CCSetter);
-    else
-      return nullptr; // Unable to find the CC setter, so unable to guarantee
-                      // that pipeline will work
-  }
-
-  return nullptr;
-}

llvm/lib/Target/ARM/ARMBaseInstrInfo.h

@@ -372,11 +372,6 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
            MI->getOpcode() == ARM::t2WhileLoopStartTP;
   }
 
-  /// Analyze loop L, which must be a single-basic-block loop, and if the
-  /// conditions can be understood enough produce a PipelinerLoopInfo object.
-  std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
-  analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override;
-
 private:
   /// Returns an unused general-purpose register which can be used for
   /// constructing an outlined call if one exists. Returns 0 otherwise.