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michaelmaitlandmichaelmaitland
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[RISCV][VLOPT] Add support for VID and VIOTA (#120331)
We already cover vid in `llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir` so no need to add tests for that instruction.
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4 files changed

+129
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‎llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -412,6 +412,8 @@ static OperandInfo getOperandInfo(const MachineOperand &MO,
412412
// Vector Compress Instruction
413413
// EMUL=LMUL. EEW=SEW.
414414
case RISCV::VCOMPRESS_VM:
415+
// Vector Element Index Instruction
416+
case RISCV::VID_V:
415417
return OperandInfo(MIVLMul, MILog2SEW);
416418

417419
// Vector Widening Integer Add/Subtract
@@ -527,6 +529,15 @@ static OperandInfo getOperandInfo(const MachineOperand &MO,
527529
return OperandInfo(RISCVVType::getEMULEqualsEEWDivSEWTimesLMUL(0, MI), 0);
528530
}
529531

532+
// Vector Iota Instruction
533+
// EEW=SEW and EMUL=LMUL, except the mask operand has EEW=1 and EMUL=
534+
// (EEW/SEW)*LMUL. Mask operand is not handled before this switch.
535+
case RISCV::VIOTA_M: {
536+
if (IsMODef || MO.getOperandNo() == 1)
537+
return OperandInfo(MIVLMul, MILog2SEW);
538+
return OperandInfo(RISCVVType::getEMULEqualsEEWDivSEWTimesLMUL(0, MI), 0);
539+
}
540+
530541
// Vector Integer Compare Instructions
531542
// Dest EEW=1 and EMUL=(EEW/SEW)*LMUL. Source EEW=SEW and EMUL=LMUL.
532543
case RISCV::VMSEQ_VI:
@@ -738,6 +749,8 @@ static bool isSupportedInstr(const MachineInstr &MI) {
738749
// vmsbf.m set-before-first mask bit
739750
// vmsif.m set-including-first mask bit
740751
// vmsof.m set-only-first mask bit
752+
// Vector Iota Instruction
753+
// Vector Element Index Instruction
741754
case RISCV::VMAND_MM:
742755
case RISCV::VMNAND_MM:
743756
case RISCV::VMANDN_MM:
@@ -749,6 +762,8 @@ static bool isSupportedInstr(const MachineInstr &MI) {
749762
case RISCV::VMSBF_M:
750763
case RISCV::VMSIF_M:
751764
case RISCV::VMSOF_M:
765+
case RISCV::VIOTA_M:
766+
case RISCV::VID_V:
752767
return true;
753768
}
754769

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector-shuffle.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -55,9 +55,9 @@ define <4 x i32> @insert_subvector_load_foldable_passthru_v4i32_v4i32(<4 x i32>
5555
define <4 x i32> @insert_subvector_add_v4i32_v4i32(<4 x i32> %v1, <4 x i32> %v2) {
5656
; CHECK-LABEL: insert_subvector_add_v4i32_v4i32:
5757
; CHECK: # %bb.0:
58-
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
58+
; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
5959
; CHECK-NEXT: vid.v v10
60-
; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma
60+
; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, ma
6161
; CHECK-NEXT: vadd.vv v8, v9, v10
6262
; CHECK-NEXT: ret
6363
%v3 = add <4 x i32> %v2, <i32 0, i32 1, i32 2, i32 3>
@@ -166,9 +166,9 @@ define <4 x i32> @insert_subvector_vp_load_v4i32_v8i32(<4 x i32> %v1, ptr %p, <8
166166
define <4 x i32> @insert_subvector_add_v4i32_v8i32(<4 x i32> %v1, <8 x i32> %v2) {
167167
; CHECK-LABEL: insert_subvector_add_v4i32_v8i32:
168168
; CHECK: # %bb.0:
169-
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
169+
; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
170170
; CHECK-NEXT: vid.v v9
171-
; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma
171+
; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, ma
172172
; CHECK-NEXT: vadd.vv v8, v10, v9
173173
; CHECK-NEXT: ret
174174
%v3 = add <8 x i32> %v2, <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>

‎llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2885,3 +2885,43 @@ define <vscale x 1 x i32> @vmsof_m(<vscale x 1 x i1> %a, <vscale x 1 x i32> %c,
28852885
%3 = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i1> %2, iXLen %vl, iXLen 0)
28862886
ret <vscale x 1 x i32> %3
28872887
}
2888+
2889+
define <vscale x 4 x i32> @viota_m(<vscale x 4 x i1> %a, <vscale x 4 x i32> %c, iXLen %vl) {
2890+
; NOVLOPT-LABEL: viota_m:
2891+
; NOVLOPT: # %bb.0:
2892+
; NOVLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma
2893+
; NOVLOPT-NEXT: viota.m v10, v0
2894+
; NOVLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
2895+
; NOVLOPT-NEXT: vadd.vv v8, v10, v8
2896+
; NOVLOPT-NEXT: ret
2897+
;
2898+
; VLOPT-LABEL: viota_m:
2899+
; VLOPT: # %bb.0:
2900+
; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
2901+
; VLOPT-NEXT: viota.m v10, v0
2902+
; VLOPT-NEXT: vadd.vv v8, v10, v8
2903+
; VLOPT-NEXT: ret
2904+
%1 = call <vscale x 4 x i32> @llvm.riscv.viota.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %a, iXLen -1)
2905+
%2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %c, iXLen %vl)
2906+
ret <vscale x 4 x i32> %2
2907+
}
2908+
2909+
define <vscale x 4 x i32> @vid.v(<vscale x 4 x i32> %c, iXLen %vl) {
2910+
; NOVLOPT-LABEL: vid.v:
2911+
; NOVLOPT: # %bb.0:
2912+
; NOVLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma
2913+
; NOVLOPT-NEXT: vid.v v10
2914+
; NOVLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
2915+
; NOVLOPT-NEXT: vadd.vv v8, v10, v8
2916+
; NOVLOPT-NEXT: ret
2917+
;
2918+
; VLOPT-LABEL: vid.v:
2919+
; VLOPT: # %bb.0:
2920+
; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
2921+
; VLOPT-NEXT: vid.v v10
2922+
; VLOPT-NEXT: vadd.vv v8, v10, v8
2923+
; VLOPT-NEXT: ret
2924+
%1 = call <vscale x 4 x i32> @llvm.riscv.vid.nxv4i32(<vscale x 4 x i32> poison, iXLen -1)
2925+
%2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %c, iXLen %vl)
2926+
ret <vscale x 4 x i32> %2
2927+
}

‎llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir

Lines changed: 70 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -892,3 +892,73 @@ body: |
892892
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
893893
%y:vr = PseudoVMV_V_V_MF2 $noreg, %x, 1, 3 /* e8 */, 0
894894
...
895+
---
896+
name: viota_m_dest
897+
body: |
898+
bb.0:
899+
; CHECK-LABEL: name: viota_m_dest
900+
; CHECK: early-clobber %x:vr = PseudoVIOTA_M_M1 $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
901+
; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
902+
%x:vr = PseudoVIOTA_M_M1 $noreg, $noreg, -1, 3 /* e8 */, 0
903+
%y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0
904+
...
905+
---
906+
name: viota_m_dest_incompatible_eew
907+
body: |
908+
bb.0:
909+
; CHECK-LABEL: name: viota_m_dest_incompatible_eew
910+
; CHECK: early-clobber %x:vr = PseudoVIOTA_M_M1 $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
911+
; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */
912+
%x:vr = PseudoVIOTA_M_M1 $noreg, $noreg, -1, 3 /* e8 */, 0
913+
%y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0
914+
...
915+
---
916+
name: viota_m_dest_incompatible_emul
917+
body: |
918+
bb.0:
919+
; CHECK-LABEL: name: viota_m_dest_incompatible_emul
920+
; CHECK: early-clobber %x:vr = PseudoVIOTA_M_M1 $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
921+
; CHECK-NEXT: %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
922+
%x:vr = PseudoVIOTA_M_M1 $noreg, $noreg, -1, 3 /* e8 */, 0
923+
%y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0
924+
...
925+
---
926+
name: viota_m_mask
927+
body: |
928+
bb.0:
929+
; CHECK-LABEL: name: viota_m_mask
930+
; CHECK: %x:vr = PseudoVMSEQ_VV_M1 $noreg, $noreg, 1, 3 /* e8 */
931+
; CHECK-NEXT: early-clobber %y:vr = PseudoVIOTA_M_M1 $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */
932+
%x:vr = PseudoVMSEQ_VV_M1 $noreg, $noreg, -1, 3 /* e8 */
933+
%y:vr = PseudoVIOTA_M_M1 $noreg, %x, 1, 3 /* e8 */, 0
934+
...
935+
---
936+
name: viota_m_mask_scale_mask
937+
body: |
938+
bb.0:
939+
; CHECK-LABEL: name: viota_m_mask_scale_mask
940+
; CHECK: early-clobber %x:vr = PseudoVMSEQ_VV_M2 $noreg, $noreg, 1, 4 /* e16 */
941+
; CHECK-NEXT: early-clobber %y:vr = PseudoVIOTA_M_M1 $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */
942+
%x:vr = PseudoVMSEQ_VV_M2 $noreg, $noreg, -1, 4 /* e16 */
943+
%y:vr = PseudoVIOTA_M_M1 $noreg, %x, 1, 3 /* e8 */, 0
944+
...
945+
---
946+
name: viota_m_mask_incompatible_emul_from_sew
947+
body: |
948+
bb.0:
949+
; CHECK-LABEL: name: viota_m_mask_incompatible_emul_from_sew
950+
; CHECK: %x:vr = PseudoVMAND_MM_B1 $noreg, $noreg, -1, 0 /* e8 */
951+
; CHECK-NEXT: early-clobber %y:vr = PseudoVIOTA_M_M1 $noreg, %x, 1, 4 /* e16 */, 0 /* tu, mu */
952+
%x:vr = PseudoVMAND_MM_B1 $noreg, $noreg, -1, 0
953+
%y:vr = PseudoVIOTA_M_M1 $noreg, %x, 1, 4 /* e16 */, 0
954+
...
955+
---
956+
name: viota_m_mask_incompatible_emul_from_lmul
957+
body: |
958+
bb.0:
959+
; CHECK-LABEL: name: viota_m_mask_incompatible_emul_from_lmul
960+
; CHECK: %x:vr = PseudoVMAND_MM_B1 $noreg, $noreg, -1, 0 /* e8 */
961+
; CHECK-NEXT: early-clobber %y:vr = PseudoVIOTA_M_MF2 $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */
962+
%x:vr = PseudoVMAND_MM_B1 $noreg, $noreg, -1, 0
963+
%y:vr = PseudoVIOTA_M_MF2 $noreg, %x, 1, 3 /* e8 */, 0
964+
...

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