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[AArch64][SVE] Instcombine SDIV to ASRD
Instcombine SDIV to ASRD when the third operand of SDIV is a power of 2 Differential Revision: https://reviews.llvm.org/D115448
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‎llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp

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@@ -1028,6 +1028,40 @@ static Optional<Instruction *> instCombineST1ScatterIndex(InstCombiner &IC,
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return None;
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}
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static Optional<Instruction *> instCombineSVESDIV(InstCombiner &IC,
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IntrinsicInst &II) {
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IRBuilder<> Builder(II.getContext());
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Builder.SetInsertPoint(&II);
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Type *Int32Ty = Builder.getInt32Ty();
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Value *Pred = II.getOperand(0);
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Value *Vec = II.getOperand(1);
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Value *DivVec = II.getOperand(2);
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Value *SplatValue = getSplatValue(DivVec);
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ConstantInt *SplatConstantInt = dyn_cast_or_null<ConstantInt>(SplatValue);
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if (!SplatConstantInt)
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return None;
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APInt Divisor = SplatConstantInt->getValue();
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if (Divisor.isPowerOf2()) {
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Constant *DivisorLog2 = ConstantInt::get(Int32Ty, Divisor.logBase2());
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auto ASRD = Builder.CreateIntrinsic(
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Intrinsic::aarch64_sve_asrd, {II.getType()}, {Pred, Vec, DivisorLog2});
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return IC.replaceInstUsesWith(II, ASRD);
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}
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if (Divisor.isNegatedPowerOf2()) {
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Divisor.negate();
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Constant *DivisorLog2 = ConstantInt::get(Int32Ty, Divisor.logBase2());
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auto ASRD = Builder.CreateIntrinsic(
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Intrinsic::aarch64_sve_asrd, {II.getType()}, {Pred, Vec, DivisorLog2});
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auto NEG = Builder.CreateIntrinsic(Intrinsic::aarch64_sve_neg,
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{ASRD->getType()}, {ASRD, Pred, ASRD});
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return IC.replaceInstUsesWith(II, NEG);
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}
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return None;
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}
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Optional<Instruction *>
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AArch64TTIImpl::instCombineIntrinsic(InstCombiner &IC,
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IntrinsicInst &II) const {
@@ -1088,6 +1122,8 @@ AArch64TTIImpl::instCombineIntrinsic(InstCombiner &IC,
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return instCombineSVELD1(IC, II, DL);
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case Intrinsic::aarch64_sve_st1:
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return instCombineSVEST1(IC, II, DL);
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case Intrinsic::aarch64_sve_sdiv:
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return instCombineSVESDIV(IC, II);
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}
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return None;

‎llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-sdiv.ll

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@@ -0,0 +1,75 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -instcombine < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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define <vscale x 4 x i32> @sdiv_i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg) #0 {
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; CHECK-LABEL: @sdiv_i32(
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; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1> [[PG:%.*]], <vscale x 4 x i32> [[A:%.*]], i32 23)
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; CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]]
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;
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 8388608, i32 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer))
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ret <vscale x 4 x i32> %out
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}
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define <vscale x 4 x i32> @sdiv_i32_neg(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg) #0 {
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; CHECK-LABEL: @sdiv_i32_neg(
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; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1> [[PG:%.*]], <vscale x 4 x i32> [[A:%.*]], i32 23)
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; CHECK-NEXT: [[TMP2:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.neg.nxv4i32(<vscale x 4 x i32> [[TMP1]], <vscale x 4 x i1> [[PG]], <vscale x 4 x i32> [[TMP1]])
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; CHECK-NEXT: ret <vscale x 4 x i32> [[TMP2]]
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;
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 -8388608, i32 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer))
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ret <vscale x 4 x i32> %out
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}
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define <vscale x 2 x i64> @sdiv_i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg) #0 {
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; CHECK-LABEL: @sdiv_i64(
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; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.asrd.nxv2i64(<vscale x 2 x i1> [[PG:%.*]], <vscale x 2 x i64> [[A:%.*]], i32 23)
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; CHECK-NEXT: ret <vscale x 2 x i64> [[TMP1]]
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;
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%out = call <vscale x 2 x i64> @llvm.aarch64.sve.sdiv.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 8388608, i64 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer))
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ret <vscale x 2 x i64> %out
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}
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define <vscale x 2 x i64> @sdiv_i64_neg(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg) #0 {
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; CHECK-LABEL: @sdiv_i64_neg(
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; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.asrd.nxv2i64(<vscale x 2 x i1> [[PG:%.*]], <vscale x 2 x i64> [[A:%.*]], i32 23)
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; CHECK-NEXT: [[TMP2:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.neg.nxv2i64(<vscale x 2 x i64> [[TMP1]], <vscale x 2 x i1> [[PG]], <vscale x 2 x i64> [[TMP1]])
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; CHECK-NEXT: ret <vscale x 2 x i64> [[TMP2]]
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;
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%out = call <vscale x 2 x i64> @llvm.aarch64.sve.sdiv.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 -8388608, i64 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer))
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ret <vscale x 2 x i64> %out
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}
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define <vscale x 4 x i32> @sdiv_i32_not_base2(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg) #0 {
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; CHECK-LABEL: @sdiv_i32_not_base2(
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; CHECK-NEXT: [[OUT:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1> [[PG:%.*]], <vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 8388607, i32 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer))
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; CHECK-NEXT: ret <vscale x 4 x i32> [[OUT]]
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;
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 8388607, i32 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer))
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ret <vscale x 4 x i32> %out
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}
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define <vscale x 4 x i32> @sdiv_i32_not_base2_neg(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg) #0 {
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; CHECK-LABEL: @sdiv_i32_not_base2_neg(
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; CHECK-NEXT: [[OUT:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1> [[PG:%.*]], <vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 -8388607, i32 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer))
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; CHECK-NEXT: ret <vscale x 4 x i32> [[OUT]]
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;
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 -8388607, i32 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer))
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ret <vscale x 4 x i32> %out
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}
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define <vscale x 4 x i32> @sdiv_i32_not_zero(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg) #0 {
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; CHECK-LABEL: @sdiv_i32_not_zero(
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; CHECK-NEXT: [[OUT:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1> [[PG:%.*]], <vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> zeroinitializer)
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; CHECK-NEXT: ret <vscale x 4 x i32> [[OUT]]
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;
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 0, i32 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer))
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ret <vscale x 4 x i32> %out
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}
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declare <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
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declare <vscale x 2 x i64> @llvm.aarch64.sve.sdiv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
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attributes #0 = { "target-features"="+sve" }

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