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4vtomat4vtomat
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[RISCV] Add missing lmul info for SiFive extensions (#76006)
1 parent 379d32d commit fb51aae

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10 files changed

+58
-56
lines changed

10 files changed

+58
-56
lines changed

‎llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -351,11 +351,13 @@ multiclass VPseudoSiFiveVMACC<string mx, VReg vd_type, VReg vs2_type,
351351

352352
multiclass VPseudoSiFiveVQMACC<string Constraint = ""> {
353353
foreach m = MxListVF8 in
354+
let VLMul = m.value in
354355
defm NAME : VPseudoSiFiveVMACC<m.MX, m.vrclass, m.vrclass, Constraint>;
355356
}
356357

357358
multiclass VPseudoSiFiveVFWMACC<string Constraint = ""> {
358359
foreach m = MxListFW in
360+
let VLMul = m.value in
359361
defm NAME : VPseudoSiFiveVMACC<m.MX, m.wvrclass, m.vrclass, Constraint>;
360362
}
361363

‎llvm/test/CodeGen/RISCV/rvv/sf_vfwmacc_4x4x4.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@ declare <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1b
1313
define <vscale x 1 x float> @intrinsic_vfwmacc_4x4x4_tu_f32mf2(<vscale x 1 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 1 x bfloat> %2, iXLen %3) nounwind {
1414
; CHECK-LABEL: intrinsic_vfwmacc_4x4x4_tu_f32mf2:
1515
; CHECK: # %bb.0: # %entry
16-
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
16+
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
1717
; CHECK-NEXT: sf.vfwmacc.4x4x4 v8, v9, v10
1818
; CHECK-NEXT: ret
1919
entry:
@@ -29,7 +29,7 @@ entry:
2929
define <vscale x 1 x float> @intrinsic_vfwmacc_4x4x4_ta_f32mf2(<vscale x 1 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 1 x bfloat> %2, iXLen %3) nounwind {
3030
; CHECK-LABEL: intrinsic_vfwmacc_4x4x4_ta_f32mf2:
3131
; CHECK: # %bb.0: # %entry
32-
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
32+
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
3333
; CHECK-NEXT: sf.vfwmacc.4x4x4 v8, v9, v10
3434
; CHECK-NEXT: ret
3535
entry:
@@ -51,7 +51,7 @@ declare <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2b
5151
define <vscale x 2 x float> @intrinsic_vfwmacc_4x4x4_tu_f32m1(<vscale x 2 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 2 x bfloat> %2, iXLen %3) nounwind {
5252
; CHECK-LABEL: intrinsic_vfwmacc_4x4x4_tu_f32m1:
5353
; CHECK: # %bb.0: # %entry
54-
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
54+
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
5555
; CHECK-NEXT: sf.vfwmacc.4x4x4 v8, v9, v10
5656
; CHECK-NEXT: ret
5757
entry:
@@ -67,7 +67,7 @@ entry:
6767
define <vscale x 2 x float> @intrinsic_vfwmacc_4x4x4_ta_f32m1(<vscale x 2 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 2 x bfloat> %2, iXLen %3) nounwind {
6868
; CHECK-LABEL: intrinsic_vfwmacc_4x4x4_ta_f32m1:
6969
; CHECK: # %bb.0: # %entry
70-
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
70+
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
7171
; CHECK-NEXT: sf.vfwmacc.4x4x4 v8, v9, v10
7272
; CHECK-NEXT: ret
7373
entry:
@@ -127,7 +127,7 @@ declare <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8b
127127
define <vscale x 8 x float> @intrinsic_vfwmacc_4x4x4_tu_f32m4(<vscale x 8 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 8 x bfloat> %2, iXLen %3) nounwind {
128128
; CHECK-LABEL: intrinsic_vfwmacc_4x4x4_tu_f32m4:
129129
; CHECK: # %bb.0: # %entry
130-
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
130+
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
131131
; CHECK-NEXT: sf.vfwmacc.4x4x4 v8, v12, v14
132132
; CHECK-NEXT: ret
133133
entry:
@@ -143,7 +143,7 @@ entry:
143143
define <vscale x 8 x float> @intrinsic_vfwmacc_4x4x4_ta_f32m4(<vscale x 8 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 8 x bfloat> %2, iXLen %3) nounwind {
144144
; CHECK-LABEL: intrinsic_vfwmacc_4x4x4_ta_f32m4:
145145
; CHECK: # %bb.0: # %entry
146-
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
146+
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
147147
; CHECK-NEXT: sf.vfwmacc.4x4x4 v8, v12, v14
148148
; CHECK-NEXT: ret
149149
entry:
@@ -165,7 +165,7 @@ declare <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv
165165
define <vscale x 16 x float> @intrinsic_vfwmacc_4x4x4_tu_f32m8(<vscale x 16 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 16 x bfloat> %2, iXLen %3) nounwind {
166166
; CHECK-LABEL: intrinsic_vfwmacc_4x4x4_tu_f32m8:
167167
; CHECK: # %bb.0: # %entry
168-
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
168+
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma
169169
; CHECK-NEXT: sf.vfwmacc.4x4x4 v8, v16, v20
170170
; CHECK-NEXT: ret
171171
entry:
@@ -181,7 +181,7 @@ entry:
181181
define <vscale x 16 x float> @intrinsic_vfwmacc_4x4x4_ta_f32m8(<vscale x 16 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 16 x bfloat> %2, iXLen %3) nounwind {
182182
; CHECK-LABEL: intrinsic_vfwmacc_4x4x4_ta_f32m8:
183183
; CHECK: # %bb.0: # %entry
184-
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
184+
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
185185
; CHECK-NEXT: sf.vfwmacc.4x4x4 v8, v16, v20
186186
; CHECK-NEXT: ret
187187
entry:

‎llvm/test/CodeGen/RISCV/rvv/sf_vqmacc_2x8x2.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,7 @@ declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8(
5151
define <vscale x 4 x i32> @intrinsic_vqmacc_2x8x2_tu_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
5252
; CHECK-LABEL: intrinsic_vqmacc_2x8x2_tu_i32m2:
5353
; CHECK: # %bb.0: # %entry
54-
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
54+
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, ma
5555
; CHECK-NEXT: sf.vqmacc.2x8x2 v8, v10, v12
5656
; CHECK-NEXT: ret
5757
entry:
@@ -67,7 +67,7 @@ entry:
6767
define <vscale x 4 x i32> @intrinsic_vqmacc_2x8x2_ta_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
6868
; CHECK-LABEL: intrinsic_vqmacc_2x8x2_ta_i32m2:
6969
; CHECK: # %bb.0: # %entry
70-
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
70+
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
7171
; CHECK-NEXT: sf.vqmacc.2x8x2 v8, v10, v12
7272
; CHECK-NEXT: ret
7373
entry:
@@ -89,7 +89,7 @@ declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8(
8989
define <vscale x 8 x i32> @intrinsic_vqmacc_2x8x2_tu_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
9090
; CHECK-LABEL: intrinsic_vqmacc_2x8x2_tu_i32m4:
9191
; CHECK: # %bb.0: # %entry
92-
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
92+
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, ma
9393
; CHECK-NEXT: sf.vqmacc.2x8x2 v8, v12, v16
9494
; CHECK-NEXT: ret
9595
entry:
@@ -105,7 +105,7 @@ entry:
105105
define <vscale x 8 x i32> @intrinsic_vqmacc_2x8x2_ta_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
106106
; CHECK-LABEL: intrinsic_vqmacc_2x8x2_ta_i32m4:
107107
; CHECK: # %bb.0: # %entry
108-
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
108+
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
109109
; CHECK-NEXT: sf.vqmacc.2x8x2 v8, v12, v16
110110
; CHECK-NEXT: ret
111111
entry:
@@ -128,7 +128,7 @@ define <vscale x 16 x i32> @intrinsic_vqmacc_2x8x2_tu_i32m8(<vscale x 16 x i32>
128128
; CHECK-LABEL: intrinsic_vqmacc_2x8x2_tu_i32m8:
129129
; CHECK: # %bb.0: # %entry
130130
; CHECK-NEXT: vl8r.v v24, (a0)
131-
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma
131+
; CHECK-NEXT: vsetvli zero, a1, e8, m8, tu, ma
132132
; CHECK-NEXT: sf.vqmacc.2x8x2 v8, v16, v24
133133
; CHECK-NEXT: ret
134134
entry:
@@ -145,7 +145,7 @@ define <vscale x 16 x i32> @intrinsic_vqmacc_2x8x2_ta_i32m8(<vscale x 16 x i32>
145145
; CHECK-LABEL: intrinsic_vqmacc_2x8x2_ta_i32m8:
146146
; CHECK: # %bb.0: # %entry
147147
; CHECK-NEXT: vl8r.v v24, (a0)
148-
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
148+
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
149149
; CHECK-NEXT: sf.vqmacc.2x8x2 v8, v16, v24
150150
; CHECK-NEXT: ret
151151
entry:

‎llvm/test/CodeGen/RISCV/rvv/sf_vqmacc_4x8x4.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,7 @@ declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv16i8(
5151
define <vscale x 4 x i32> @intrinsic_vqmacc_4x8x4_tu_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
5252
; CHECK-LABEL: intrinsic_vqmacc_4x8x4_tu_i32m2:
5353
; CHECK: # %bb.0: # %entry
54-
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
54+
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, ma
5555
; CHECK-NEXT: sf.vqmacc.4x8x4 v8, v10, v12
5656
; CHECK-NEXT: ret
5757
entry:
@@ -67,7 +67,7 @@ entry:
6767
define <vscale x 4 x i32> @intrinsic_vqmacc_4x8x4_ta_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
6868
; CHECK-LABEL: intrinsic_vqmacc_4x8x4_ta_i32m2:
6969
; CHECK: # %bb.0: # %entry
70-
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
70+
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
7171
; CHECK-NEXT: sf.vqmacc.4x8x4 v8, v10, v12
7272
; CHECK-NEXT: ret
7373
entry:
@@ -89,7 +89,7 @@ declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv32i8(
8989
define <vscale x 8 x i32> @intrinsic_vqmacc_4x8x4_tu_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
9090
; CHECK-LABEL: intrinsic_vqmacc_4x8x4_tu_i32m4:
9191
; CHECK: # %bb.0: # %entry
92-
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
92+
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, ma
9393
; CHECK-NEXT: sf.vqmacc.4x8x4 v8, v12, v16
9494
; CHECK-NEXT: ret
9595
entry:
@@ -105,7 +105,7 @@ entry:
105105
define <vscale x 8 x i32> @intrinsic_vqmacc_4x8x4_ta_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
106106
; CHECK-LABEL: intrinsic_vqmacc_4x8x4_ta_i32m4:
107107
; CHECK: # %bb.0: # %entry
108-
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
108+
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
109109
; CHECK-NEXT: sf.vqmacc.4x8x4 v8, v12, v16
110110
; CHECK-NEXT: ret
111111
entry:
@@ -128,7 +128,7 @@ define <vscale x 16 x i32> @intrinsic_vqmacc_4x8x4_tu_i32m8(<vscale x 16 x i32>
128128
; CHECK-LABEL: intrinsic_vqmacc_4x8x4_tu_i32m8:
129129
; CHECK: # %bb.0: # %entry
130130
; CHECK-NEXT: vl8r.v v24, (a0)
131-
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma
131+
; CHECK-NEXT: vsetvli zero, a1, e8, m8, tu, ma
132132
; CHECK-NEXT: sf.vqmacc.4x8x4 v8, v16, v24
133133
; CHECK-NEXT: ret
134134
entry:
@@ -145,7 +145,7 @@ define <vscale x 16 x i32> @intrinsic_vqmacc_4x8x4_ta_i32m8(<vscale x 16 x i32>
145145
; CHECK-LABEL: intrinsic_vqmacc_4x8x4_ta_i32m8:
146146
; CHECK: # %bb.0: # %entry
147147
; CHECK-NEXT: vl8r.v v24, (a0)
148-
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
148+
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
149149
; CHECK-NEXT: sf.vqmacc.4x8x4 v8, v16, v24
150150
; CHECK-NEXT: ret
151151
entry:

‎llvm/test/CodeGen/RISCV/rvv/sf_vqmaccsu_2x8x2.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,7 @@ declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8(
5151
define <vscale x 4 x i32> @intrinsic_vqmaccsu_2x8x2_tu_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
5252
; CHECK-LABEL: intrinsic_vqmaccsu_2x8x2_tu_i32m2:
5353
; CHECK: # %bb.0: # %entry
54-
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
54+
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, ma
5555
; CHECK-NEXT: sf.vqmaccsu.2x8x2 v8, v10, v12
5656
; CHECK-NEXT: ret
5757
entry:
@@ -67,7 +67,7 @@ entry:
6767
define <vscale x 4 x i32> @intrinsic_vqmaccsu_2x8x2_ta_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
6868
; CHECK-LABEL: intrinsic_vqmaccsu_2x8x2_ta_i32m2:
6969
; CHECK: # %bb.0: # %entry
70-
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
70+
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
7171
; CHECK-NEXT: sf.vqmaccsu.2x8x2 v8, v10, v12
7272
; CHECK-NEXT: ret
7373
entry:
@@ -89,7 +89,7 @@ declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8(
8989
define <vscale x 8 x i32> @intrinsic_vqmaccsu_2x8x2_tu_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
9090
; CHECK-LABEL: intrinsic_vqmaccsu_2x8x2_tu_i32m4:
9191
; CHECK: # %bb.0: # %entry
92-
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
92+
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, ma
9393
; CHECK-NEXT: sf.vqmaccsu.2x8x2 v8, v12, v16
9494
; CHECK-NEXT: ret
9595
entry:
@@ -105,7 +105,7 @@ entry:
105105
define <vscale x 8 x i32> @intrinsic_vqmaccsu_2x8x2_ta_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
106106
; CHECK-LABEL: intrinsic_vqmaccsu_2x8x2_ta_i32m4:
107107
; CHECK: # %bb.0: # %entry
108-
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
108+
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
109109
; CHECK-NEXT: sf.vqmaccsu.2x8x2 v8, v12, v16
110110
; CHECK-NEXT: ret
111111
entry:
@@ -128,7 +128,7 @@ define <vscale x 16 x i32> @intrinsic_vqmaccsu_2x8x2_tu_i32m8(<vscale x 16 x i32
128128
; CHECK-LABEL: intrinsic_vqmaccsu_2x8x2_tu_i32m8:
129129
; CHECK: # %bb.0: # %entry
130130
; CHECK-NEXT: vl8r.v v24, (a0)
131-
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma
131+
; CHECK-NEXT: vsetvli zero, a1, e8, m8, tu, ma
132132
; CHECK-NEXT: sf.vqmaccsu.2x8x2 v8, v16, v24
133133
; CHECK-NEXT: ret
134134
entry:
@@ -145,7 +145,7 @@ define <vscale x 16 x i32> @intrinsic_vqmaccsu_2x8x2_ta_i32m8(<vscale x 16 x i32
145145
; CHECK-LABEL: intrinsic_vqmaccsu_2x8x2_ta_i32m8:
146146
; CHECK: # %bb.0: # %entry
147147
; CHECK-NEXT: vl8r.v v24, (a0)
148-
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
148+
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
149149
; CHECK-NEXT: sf.vqmaccsu.2x8x2 v8, v16, v24
150150
; CHECK-NEXT: ret
151151
entry:

‎llvm/test/CodeGen/RISCV/rvv/sf_vqmaccsu_4x8x4.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,7 @@ declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv16i8(
5151
define <vscale x 4 x i32> @intrinsic_vqmaccsu_4x8x4_tu_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
5252
; CHECK-LABEL: intrinsic_vqmaccsu_4x8x4_tu_i32m2:
5353
; CHECK: # %bb.0: # %entry
54-
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
54+
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, ma
5555
; CHECK-NEXT: sf.vqmaccsu.4x8x4 v8, v10, v12
5656
; CHECK-NEXT: ret
5757
entry:
@@ -67,7 +67,7 @@ entry:
6767
define <vscale x 4 x i32> @intrinsic_vqmaccsu_4x8x4_ta_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
6868
; CHECK-LABEL: intrinsic_vqmaccsu_4x8x4_ta_i32m2:
6969
; CHECK: # %bb.0: # %entry
70-
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
70+
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
7171
; CHECK-NEXT: sf.vqmaccsu.4x8x4 v8, v10, v12
7272
; CHECK-NEXT: ret
7373
entry:
@@ -89,7 +89,7 @@ declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv32i8(
8989
define <vscale x 8 x i32> @intrinsic_vqmaccsu_4x8x4_tu_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
9090
; CHECK-LABEL: intrinsic_vqmaccsu_4x8x4_tu_i32m4:
9191
; CHECK: # %bb.0: # %entry
92-
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
92+
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, ma
9393
; CHECK-NEXT: sf.vqmaccsu.4x8x4 v8, v12, v16
9494
; CHECK-NEXT: ret
9595
entry:
@@ -105,7 +105,7 @@ entry:
105105
define <vscale x 8 x i32> @intrinsic_vqmaccsu_4x8x4_ta_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
106106
; CHECK-LABEL: intrinsic_vqmaccsu_4x8x4_ta_i32m4:
107107
; CHECK: # %bb.0: # %entry
108-
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
108+
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
109109
; CHECK-NEXT: sf.vqmaccsu.4x8x4 v8, v12, v16
110110
; CHECK-NEXT: ret
111111
entry:
@@ -128,7 +128,7 @@ define <vscale x 16 x i32> @intrinsic_vqmaccsu_4x8x4_tu_i32m8(<vscale x 16 x i32
128128
; CHECK-LABEL: intrinsic_vqmaccsu_4x8x4_tu_i32m8:
129129
; CHECK: # %bb.0: # %entry
130130
; CHECK-NEXT: vl8r.v v24, (a0)
131-
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma
131+
; CHECK-NEXT: vsetvli zero, a1, e8, m8, tu, ma
132132
; CHECK-NEXT: sf.vqmaccsu.4x8x4 v8, v16, v24
133133
; CHECK-NEXT: ret
134134
entry:
@@ -145,7 +145,7 @@ define <vscale x 16 x i32> @intrinsic_vqmaccsu_4x8x4_ta_i32m8(<vscale x 16 x i32
145145
; CHECK-LABEL: intrinsic_vqmaccsu_4x8x4_ta_i32m8:
146146
; CHECK: # %bb.0: # %entry
147147
; CHECK-NEXT: vl8r.v v24, (a0)
148-
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
148+
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
149149
; CHECK-NEXT: sf.vqmaccsu.4x8x4 v8, v16, v24
150150
; CHECK-NEXT: ret
151151
entry:

‎llvm/test/CodeGen/RISCV/rvv/sf_vqmaccu_2x8x2.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,7 @@ declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8(
5151
define <vscale x 4 x i32> @intrinsic_vqmaccu_2x8x2_tu_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
5252
; CHECK-LABEL: intrinsic_vqmaccu_2x8x2_tu_i32m2:
5353
; CHECK: # %bb.0: # %entry
54-
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
54+
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, ma
5555
; CHECK-NEXT: sf.vqmaccu.2x8x2 v8, v10, v12
5656
; CHECK-NEXT: ret
5757
entry:
@@ -67,7 +67,7 @@ entry:
6767
define <vscale x 4 x i32> @intrinsic_vqmaccu_2x8x2_ta_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
6868
; CHECK-LABEL: intrinsic_vqmaccu_2x8x2_ta_i32m2:
6969
; CHECK: # %bb.0: # %entry
70-
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
70+
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
7171
; CHECK-NEXT: sf.vqmaccu.2x8x2 v8, v10, v12
7272
; CHECK-NEXT: ret
7373
entry:
@@ -89,7 +89,7 @@ declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8(
8989
define <vscale x 8 x i32> @intrinsic_vqmaccu_2x8x2_tu_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
9090
; CHECK-LABEL: intrinsic_vqmaccu_2x8x2_tu_i32m4:
9191
; CHECK: # %bb.0: # %entry
92-
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
92+
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, ma
9393
; CHECK-NEXT: sf.vqmaccu.2x8x2 v8, v12, v16
9494
; CHECK-NEXT: ret
9595
entry:
@@ -105,7 +105,7 @@ entry:
105105
define <vscale x 8 x i32> @intrinsic_vqmaccu_2x8x2_ta_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
106106
; CHECK-LABEL: intrinsic_vqmaccu_2x8x2_ta_i32m4:
107107
; CHECK: # %bb.0: # %entry
108-
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
108+
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
109109
; CHECK-NEXT: sf.vqmaccu.2x8x2 v8, v12, v16
110110
; CHECK-NEXT: ret
111111
entry:
@@ -128,7 +128,7 @@ define <vscale x 16 x i32> @intrinsic_vqmaccu_2x8x2_tu_i32m8(<vscale x 16 x i32>
128128
; CHECK-LABEL: intrinsic_vqmaccu_2x8x2_tu_i32m8:
129129
; CHECK: # %bb.0: # %entry
130130
; CHECK-NEXT: vl8r.v v24, (a0)
131-
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma
131+
; CHECK-NEXT: vsetvli zero, a1, e8, m8, tu, ma
132132
; CHECK-NEXT: sf.vqmaccu.2x8x2 v8, v16, v24
133133
; CHECK-NEXT: ret
134134
entry:
@@ -145,7 +145,7 @@ define <vscale x 16 x i32> @intrinsic_vqmaccu_2x8x2_ta_i32m8(<vscale x 16 x i32>
145145
; CHECK-LABEL: intrinsic_vqmaccu_2x8x2_ta_i32m8:
146146
; CHECK: # %bb.0: # %entry
147147
; CHECK-NEXT: vl8r.v v24, (a0)
148-
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
148+
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
149149
; CHECK-NEXT: sf.vqmaccu.2x8x2 v8, v16, v24
150150
; CHECK-NEXT: ret
151151
entry:

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