Responding to review comments

Change-Id: Ic1b7f8774ae529680597b4e032c4a63416ac927a

Author: nasherm

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

@@ -547,8 +547,11 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
   setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Custom);
   setOperationAction(ISD::STRICT_FP_ROUND, MVT::f64, Custom);
 
-  if (Subtarget->hasFPARMv8())
-    setOperationAction(ISD::FP_ROUND, MVT::f16, Custom);
+  if (Subtarget->hasFPARMv8()) {
+    setOperationAction(ISD::BITCAST, MVT::i16, Custom);
+    setOperationAction(ISD::BITCAST, MVT::f16, Custom);
+    setOperationAction(ISD::BITCAST, MVT::bf16, Custom);
+  }
 
   setOperationAction(ISD::FP_TO_UINT_SAT, MVT::i32, Custom);
   setOperationAction(ISD::FP_TO_UINT_SAT, MVT::i64, Custom);
@@ -24617,8 +24620,8 @@ void AArch64TargetLowering::ReplaceBITCASTResults(
   EVT VT = N->getValueType(0);
   EVT SrcVT = Op.getValueType();
 
-  // Default to the generic legalizer
-  if (SrcVT == MVT::f16 && !Subtarget->hasFPARMv8())
+  if (!Subtarget->hasFPARMv8() &&
+      (SrcVT == MVT::f16 || SrcVT == MVT::i16 || SrcVT == MVT::bf16))
     return;
 
   if (VT == MVT::v2i16 && SrcVT == MVT::i32) {

llvm/test/CodeGen/AArch64/float16-promotion-with-nofp.ll renamed to llvm/test/CodeGen/AArch64/16bit-float-promotion-with-nofp.ll

@@ -8,13 +8,24 @@ define half @f2h(float %a) {
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    .cfi_offset w30, -16
 ; CHECK-NEXT:    bl __gnu_f2h_ieee
-; CHECK-NEXT:    and w0, w0, #0xffff
-; CHECK-NEXT:    bl __gnu_h2f_ieee
-; CHECK-NEXT:    bl __gnu_f2h_ieee
 ; CHECK-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
 entry:
   %0 = fptrunc float %a to half
   ret half %0
 }
 
+define bfloat @f2bfloat(float %a) {
+; CHECK-LABEL: f2bfloat:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    .cfi_offset w30, -16
+; CHECK-NEXT:    bl __truncsfbf2
+; CHECK-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT:    ret
+entry:
+  %0 = fptrunc float %a to bfloat
+  ret bfloat %0
+}
+