Skip to content

Commit fb94c64

Browse files
4vtomat4vtomat
authored
[RISCV][SiFive] Reduce intrinsics of SiFive VCIX extension (#79407)
This patch models LMUL and SEW as inputs in sf_vc_x_se and sf_vc_i_se, it reduces 42 intrinsics in the lookup table.
1 parent 8e01042 commit fb94c64

File tree

13 files changed

+460
-441
lines changed

13 files changed

+460
-441
lines changed

‎clang/include/clang/Basic/riscv_sifive_vector.td

Lines changed: 9 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -46,34 +46,23 @@ multiclass VCIXBuiltinSet<string name, string IR_name, string suffix,
4646
}
4747

4848
multiclass RVVVCIXBuiltinSet<list<string> range, string prototype,
49-
list<int> intrinsic_types, bit UseGPR> {
49+
list<int> intrinsic_types, bit UseGPR,
50+
string suffix = "Uv"> {
5051
foreach r = range in
5152
let RequiredFeatures = !if(!and(UseGPR, !eq(r, "l")),
5253
["Xsfvcp", "RV64"], ["Xsfvcp"]) in
53-
defm : VCIXBuiltinSet<NAME, NAME, "Uv", prototype, r, intrinsic_types>;
54+
defm : VCIXBuiltinSet<NAME, NAME, suffix, prototype, r, intrinsic_types>;
5455
}
5556

56-
multiclass RVVVCIXBuiltinSetWVType<list<string> range, string prototype,
57-
list<int> intrinsic_types, bit UseGPR> {
58-
foreach r = range in
59-
let RequiredFeatures = !if(!and(UseGPR, !eq(r, "l")),
60-
["Xsfvcp", "RV64"], ["Xsfvcp"]) in
61-
// These intrinsics don't have any vector types in the output and inputs,
62-
// but we still need to add vetvli for them. So we encode different
63-
// VTYPE into the intrinsic names, and then will know which vsetvli is
64-
// correct.
65-
foreach s = VCIXSuffix<r>.suffix in
66-
// Since we already encode the Vtype into the name, so just set
67-
// Log2LMUL to zero. Otherwise the RISCVVEmitter will expand
68-
// lots of redundant intrinsic but have same names.
69-
let Log2LMUL = [0] in
70-
def : VCIXBuiltinSet<NAME # "_u" # s, NAME # "_e" # s,
71-
"", prototype, r, intrinsic_types>;
57+
multiclass RVVVCIXBuiltinSetWOSuffix<list<string> range, string prototype,
58+
list<int> intrinsic_types, bit UseGPR> {
59+
let Log2LMUL = [0] in
60+
defm NAME : RVVVCIXBuiltinSet<range, prototype, intrinsic_types, UseGPR, "">;
7261
}
7362

7463
let SupportOverloading = false in {
75-
defm sf_vc_x_se : RVVVCIXBuiltinSetWVType<["c", "s", "i", "l"], "0KzKzKzUe", [0, 3], UseGPR=1>;
76-
defm sf_vc_i_se : RVVVCIXBuiltinSetWVType<["c", "s", "i", "l"], "0KzKzKzKz", [2, 3], UseGPR=0>;
64+
defm sf_vc_x : RVVVCIXBuiltinSetWOSuffix<["c", "s", "i", "l"], "0KzKzKzUeKzKz", [0, 3], UseGPR=1>;
65+
defm sf_vc_i : RVVVCIXBuiltinSetWOSuffix<["i"], "0KzKzKzKzKzKz", [2, 3], UseGPR=0>;
7766
defm sf_vc_xv : RVVVCIXBuiltinSet<["csi", "l"], "0KzKzUvUe", [0, 2, 3], UseGPR=1>;
7867
defm sf_vc_iv : RVVVCIXBuiltinSet<["csi", "l"], "0KzKzUvKz", [0, 2, 3], UseGPR=0>;
7968
defm sf_vc_vv : RVVVCIXBuiltinSet<["csi", "l"], "0KzKzUvUv", [0, 2, 3], UseGPR=0>;

‎clang/lib/Headers/sifive_vector.h

Lines changed: 102 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,4 +13,106 @@
1313

1414
#pragma clang riscv intrinsic sifive_vector
1515

16+
#define __riscv_sf_vc_x_se_u8mf4(p27_26, p24_20, p11_7, rs1, vl) \
17+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint8_t)rs1, 8, 6, vl)
18+
#define __riscv_sf_vc_x_se_u8mf2(p27_26, p24_20, p11_7, rs1, vl) \
19+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint8_t)rs1, 8, 7, vl)
20+
#define __riscv_sf_vc_x_se_u8m1(p27_26, p24_20, p11_7, rs1, vl) \
21+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint8_t)rs1, 8, 0, vl)
22+
#define __riscv_sf_vc_x_se_u8m2(p27_26, p24_20, p11_7, rs1, vl) \
23+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint8_t)rs1, 8, 1, vl)
24+
#define __riscv_sf_vc_x_se_u8m4(p27_26, p24_20, p11_7, rs1, vl) \
25+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint8_t)rs1, 8, 2, vl)
26+
#define __riscv_sf_vc_x_se_u8m8(p27_26, p24_20, p11_7, rs1, vl) \
27+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint8_t)rs1, 8, 3, vl)
28+
29+
#define __riscv_sf_vc_x_se_u16mf2(p27_26, p24_20, p11_7, rs1, vl) \
30+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint16_t)rs1, 16, 7, vl)
31+
#define __riscv_sf_vc_x_se_u16m1(p27_26, p24_20, p11_7, rs1, vl) \
32+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint16_t)rs1, 16, 0, vl)
33+
#define __riscv_sf_vc_x_se_u16m2(p27_26, p24_20, p11_7, rs1, vl) \
34+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint16_t)rs1, 16, 1, vl)
35+
#define __riscv_sf_vc_x_se_u16m4(p27_26, p24_20, p11_7, rs1, vl) \
36+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint16_t)rs1, 16, 2, vl)
37+
#define __riscv_sf_vc_x_se_u16m8(p27_26, p24_20, p11_7, rs1, vl) \
38+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint16_t)rs1, 16, 3, vl)
39+
40+
#define __riscv_sf_vc_x_se_u32m1(p27_26, p24_20, p11_7, rs1, vl) \
41+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint32_t)rs1, 32, 0, vl)
42+
#define __riscv_sf_vc_x_se_u32m2(p27_26, p24_20, p11_7, rs1, vl) \
43+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint32_t)rs1, 32, 1, vl)
44+
#define __riscv_sf_vc_x_se_u32m4(p27_26, p24_20, p11_7, rs1, vl) \
45+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint32_t)rs1, 32, 2, vl)
46+
#define __riscv_sf_vc_x_se_u32m8(p27_26, p24_20, p11_7, rs1, vl) \
47+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint32_t)rs1, 32, 3, vl)
48+
49+
#define __riscv_sf_vc_i_se_u8mf4(p27_26, p24_20, p11_7, simm5, vl) \
50+
__riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 8, 7, vl)
51+
#define __riscv_sf_vc_i_se_u8mf2(p27_26, p24_20, p11_7, simm5, vl) \
52+
__riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 8, 6, vl)
53+
#define __riscv_sf_vc_i_se_u8m1(p27_26, p24_20, p11_7, simm5, vl) \
54+
__riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 8, 0, vl)
55+
#define __riscv_sf_vc_i_se_u8m2(p27_26, p24_20, p11_7, simm5, vl) \
56+
__riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 8, 1, vl)
57+
#define __riscv_sf_vc_i_se_u8m4(p27_26, p24_20, p11_7, simm5, vl) \
58+
__riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 8, 2, vl)
59+
#define __riscv_sf_vc_i_se_u8m8(p27_26, p24_20, p11_7, simm5, vl) \
60+
__riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 8, 3, vl)
61+
62+
#define __riscv_sf_vc_i_se_u16mf2(p27_26, p24_20, p11_7, simm5, vl) \
63+
__riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 16, 7, vl)
64+
#define __riscv_sf_vc_i_se_u16m1(p27_26, p24_20, p11_7, simm5, vl) \
65+
__riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 16, 0, vl)
66+
#define __riscv_sf_vc_i_se_u16m2(p27_26, p24_20, p11_7, simm5, vl) \
67+
__riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 16, 1, vl)
68+
#define __riscv_sf_vc_i_se_u16m4(p27_26, p24_20, p11_7, simm5, vl) \
69+
__riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 16, 2, vl)
70+
#define __riscv_sf_vc_i_se_u16m8(p27_26, p24_20, p11_7, simm5, vl) \
71+
__riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 16, 3, vl)
72+
73+
#define __riscv_sf_vc_i_se_u32m1(p27_26, p24_20, p11_7, simm5, vl) \
74+
__riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 32, 0, vl)
75+
#define __riscv_sf_vc_i_se_u32m2(p27_26, p24_20, p11_7, simm5, vl) \
76+
__riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 32, 1, vl)
77+
#define __riscv_sf_vc_i_se_u32m4(p27_26, p24_20, p11_7, simm5, vl) \
78+
__riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 32, 2, vl)
79+
#define __riscv_sf_vc_i_se_u32m8(p27_26, p24_20, p11_7, simm5, vl) \
80+
__riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 32, 3, vl)
81+
82+
#if __riscv_v_elen >= 64
83+
#define __riscv_sf_vc_x_se_u8mf8(p27_26, p24_20, p11_7, rs1, vl) \
84+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint8_t)rs1, 8, 5, vl)
85+
#define __riscv_sf_vc_x_se_u16mf4(p27_26, p24_20, p11_7, rs1, vl) \
86+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint16_t)rs1, 16, 6, vl)
87+
#define __riscv_sf_vc_x_se_u32mf2(p27_26, p24_20, p11_7, rs1, vl) \
88+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint32_t)rs1, 32, 7, vl)
89+
90+
#define __riscv_sf_vc_i_se_u8mf8(p27_26, p24_20, p11_7, simm5, vl) \
91+
__riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 8, 5, vl)
92+
#define __riscv_sf_vc_i_se_u16mf4(p27_26, p24_20, p11_7, simm5, vl) \
93+
__riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 16, 6, vl)
94+
#define __riscv_sf_vc_i_se_u32mf2(p27_26, p24_20, p11_7, simm5, vl) \
95+
__riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 32, 7, vl)
96+
97+
#define __riscv_sf_vc_i_se_u64m1(p27_26, p24_20, p11_7, simm5, vl) \
98+
__riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 64, 0, vl)
99+
#define __riscv_sf_vc_i_se_u64m2(p27_26, p24_20, p11_7, simm5, vl) \
100+
__riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 64, 1, vl)
101+
#define __riscv_sf_vc_i_se_u64m4(p27_26, p24_20, p11_7, simm5, vl) \
102+
__riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 64, 2, vl)
103+
#define __riscv_sf_vc_i_se_u64m8(p27_26, p24_20, p11_7, simm5, vl) \
104+
__riscv_sf_vc_i_se(p27_26, p24_20, p11_7, simm5, 64, 3, vl)
105+
106+
#if __riscv_xlen >= 64
107+
#define __riscv_sf_vc_x_se_u64m1(p27_26, p24_20, p11_7, rs1, vl) \
108+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint64_t)rs1, 64, 0, vl)
109+
#define __riscv_sf_vc_x_se_u64m2(p27_26, p24_20, p11_7, rs1, vl) \
110+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint64_t)rs1, 64, 1, vl)
111+
#define __riscv_sf_vc_x_se_u64m4(p27_26, p24_20, p11_7, rs1, vl) \
112+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint64_t)rs1, 64, 2, vl)
113+
#define __riscv_sf_vc_x_se_u64m8(p27_26, p24_20, p11_7, rs1, vl) \
114+
__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint64_t)rs1, 64, 3, vl)
115+
#endif
116+
#endif
117+
16118
#endif //_SIFIVE_VECTOR_H_

‎clang/lib/Sema/SemaChecking.cpp

Lines changed: 8 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -5441,33 +5441,13 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI,
54415441
CheckInvalidVLENandLMUL(TI, TheCall, *this, Op3Type, ElemSize * 4);
54425442
}
54435443

5444-
case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u8mf8:
5445-
case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u8mf4:
5446-
case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u8mf2:
5447-
case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u8m1:
5448-
case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u8m2:
5449-
case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u8m4:
5450-
case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u8m8:
5451-
case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u16mf4:
5452-
case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u16mf2:
5453-
case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u16m1:
5454-
case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u16m2:
5455-
case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u16m4:
5456-
case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u16m8:
5457-
case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u32mf2:
5458-
case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u32m1:
5459-
case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u32m2:
5460-
case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u32m4:
5461-
case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u32m8:
5462-
case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u64m1:
5463-
case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u64m2:
5464-
case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u64m4:
5465-
case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u64m8:
5466-
// bit_27_26, bit_24_20, bit_11_7, simm5
5444+
case RISCVVector::BI__builtin_rvv_sf_vc_i_se:
5445+
// bit_27_26, bit_24_20, bit_11_7, simm5, sew, log2lmul
54675446
return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) ||
54685447
SemaBuiltinConstantArgRange(TheCall, 1, 0, 31) ||
54695448
SemaBuiltinConstantArgRange(TheCall, 2, 0, 31) ||
5470-
SemaBuiltinConstantArgRange(TheCall, 3, -16, 15);
5449+
SemaBuiltinConstantArgRange(TheCall, 3, -16, 15) ||
5450+
CheckRISCVLMUL(TheCall, 5);
54715451
case RISCVVector::BI__builtin_rvv_sf_vc_iv_se:
54725452
// bit_27_26, bit_11_7, vs2, simm5
54735453
return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) ||
@@ -5493,32 +5473,12 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI,
54935473
// bit_27_26, vd, vs2, simm5
54945474
return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) ||
54955475
SemaBuiltinConstantArgRange(TheCall, 3, -16, 15);
5496-
case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u8mf8:
5497-
case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u8mf4:
5498-
case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u8mf2:
5499-
case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u8m1:
5500-
case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u8m2:
5501-
case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u8m4:
5502-
case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u8m8:
5503-
case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u16mf4:
5504-
case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u16mf2:
5505-
case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u16m1:
5506-
case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u16m2:
5507-
case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u16m4:
5508-
case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u16m8:
5509-
case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u32mf2:
5510-
case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u32m1:
5511-
case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u32m2:
5512-
case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u32m4:
5513-
case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u32m8:
5514-
case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u64m1:
5515-
case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u64m2:
5516-
case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u64m4:
5517-
case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u64m8:
5518-
// bit_27_26, bit_24_20, bit_11_7, xs1
5476+
case RISCVVector::BI__builtin_rvv_sf_vc_x_se:
5477+
// bit_27_26, bit_24_20, bit_11_7, xs1, sew, log2lmul
55195478
return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) ||
55205479
SemaBuiltinConstantArgRange(TheCall, 1, 0, 31) ||
5521-
SemaBuiltinConstantArgRange(TheCall, 2, 0, 31);
5480+
SemaBuiltinConstantArgRange(TheCall, 2, 0, 31) ||
5481+
CheckRISCVLMUL(TheCall, 5);
55225482
case RISCVVector::BI__builtin_rvv_sf_vc_xv_se:
55235483
case RISCVVector::BI__builtin_rvv_sf_vc_vv_se:
55245484
// bit_27_26, bit_11_7, vs2, xs1/vs1

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-x-rv64.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@
1010

1111
// CHECK-RV64-LABEL: @test_sf_vc_x_se_u64m1(
1212
// CHECK-RV64-NEXT: entry:
13-
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.e64m1.i64.i64.i64(i64 3, i64 31, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]])
13+
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 [[RS1:%.*]], i64 64, i64 0, i64 [[VL:%.*]])
1414
// CHECK-RV64-NEXT: ret void
1515
//
1616
void test_sf_vc_x_se_u64m1(uint64_t rs1, size_t vl) {
@@ -19,7 +19,7 @@ void test_sf_vc_x_se_u64m1(uint64_t rs1, size_t vl) {
1919

2020
// CHECK-RV64-LABEL: @test_sf_vc_x_se_u64m2(
2121
// CHECK-RV64-NEXT: entry:
22-
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.e64m2.i64.i64.i64(i64 3, i64 31, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]])
22+
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 [[RS1:%.*]], i64 64, i64 1, i64 [[VL:%.*]])
2323
// CHECK-RV64-NEXT: ret void
2424
//
2525
void test_sf_vc_x_se_u64m2(uint64_t rs1, size_t vl) {
@@ -28,7 +28,7 @@ void test_sf_vc_x_se_u64m2(uint64_t rs1, size_t vl) {
2828

2929
// CHECK-RV64-LABEL: @test_sf_vc_x_se_u64m4(
3030
// CHECK-RV64-NEXT: entry:
31-
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.e64m4.i64.i64.i64(i64 3, i64 31, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]])
31+
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 [[RS1:%.*]], i64 64, i64 2, i64 [[VL:%.*]])
3232
// CHECK-RV64-NEXT: ret void
3333
//
3434
void test_sf_vc_x_se_u64m4(uint64_t rs1, size_t vl) {
@@ -37,7 +37,7 @@ void test_sf_vc_x_se_u64m4(uint64_t rs1, size_t vl) {
3737

3838
// CHECK-RV64-LABEL: @test_sf_vc_x_se_u64m8(
3939
// CHECK-RV64-NEXT: entry:
40-
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.e64m8.i64.i64.i64(i64 3, i64 31, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]])
40+
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 [[RS1:%.*]], i64 64, i64 3, i64 [[VL:%.*]])
4141
// CHECK-RV64-NEXT: ret void
4242
//
4343
void test_sf_vc_x_se_u64m8(uint64_t rs1, size_t vl) {

0 commit comments

Comments
 (0)