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Revert "[SLP][TTI][X86]Add addsub pattern cost estimation. (#76461)"
This reverts commit bc8c4bb. Change is failing to build on several bots: - https://lab.llvm.org/buildbot/#/builders/127/builds/60184 - https://lab.llvm.org/buildbot/#/builders/123/builds/23709 - https://lab.llvm.org/buildbot/#/builders/216/builds/32302
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+19
-94
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8 files changed

+19
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lines changed

‎llvm/include/llvm/Analysis/TargetTransformInfo.h

Lines changed: 0 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -1243,18 +1243,6 @@ class TargetTransformInfo {
12431243
ArrayRef<const Value *> Args = ArrayRef<const Value *>(),
12441244
const Instruction *CxtI = nullptr) const;
12451245

1246-
/// Returns the cost estimation for alternating opcode pattern that can be
1247-
/// lowered to a single instruction on the target. In X86 this is for the
1248-
/// addsub instruction which corrsponds to a Shuffle + Fadd + FSub pattern in
1249-
/// IR. This function expects two opcodes: \p Opcode1 and \p Opcode2 being
1250-
/// selected by \p OpcodeMask. The mask contains one bit per lane and is a `0`
1251-
/// when \p Opcode0 is selected and `1` when Opcode1 is selected.
1252-
/// \p VecTy is the vector type of the instruction to be generated.
1253-
InstructionCost getAltInstrCost(
1254-
VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
1255-
const SmallBitVector &OpcodeMask,
1256-
TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput) const;
1257-
12581246
/// \return The cost of a shuffle instruction of kind Kind and of type Tp.
12591247
/// The exact mask may be passed as Mask, or else the array will be empty.
12601248
/// The index and subtype parameters are used by the subvector insertion and
@@ -1956,10 +1944,6 @@ class TargetTransformInfo::Concept {
19561944
unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
19571945
OperandValueInfo Opd1Info, OperandValueInfo Opd2Info,
19581946
ArrayRef<const Value *> Args, const Instruction *CxtI = nullptr) = 0;
1959-
virtual InstructionCost getAltInstrCost(
1960-
VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
1961-
const SmallBitVector &OpcodeMask,
1962-
TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput) const = 0;
19631947

19641948
virtual InstructionCost getShuffleCost(ShuffleKind Kind, VectorType *Tp,
19651949
ArrayRef<int> Mask,
@@ -2571,12 +2555,6 @@ class TargetTransformInfo::Model final : public TargetTransformInfo::Concept {
25712555
return Impl.getArithmeticInstrCost(Opcode, Ty, CostKind, Opd1Info, Opd2Info,
25722556
Args, CxtI);
25732557
}
2574-
InstructionCost getAltInstrCost(VectorType *VecTy, unsigned Opcode0,
2575-
unsigned Opcode1,
2576-
const SmallBitVector &OpcodeMask,
2577-
TTI::TargetCostKind CostKind) const override {
2578-
return Impl.getAltInstrCost(VecTy, Opcode0, Opcode1, OpcodeMask, CostKind);
2579-
}
25802558

25812559
InstructionCost getShuffleCost(ShuffleKind Kind, VectorType *Tp,
25822560
ArrayRef<int> Mask,

‎llvm/include/llvm/Analysis/TargetTransformInfoImpl.h

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -554,13 +554,6 @@ class TargetTransformInfoImplBase {
554554
return 1;
555555
}
556556

557-
InstructionCost getAltInstrCost(VectorType *VecTy, unsigned Opcode0,
558-
unsigned Opcode1,
559-
const SmallBitVector &OpcodeMask,
560-
TTI::TargetCostKind CostKind) const {
561-
return InstructionCost::getInvalid();
562-
}
563-
564557
InstructionCost
565558
getShuffleCost(TTI::ShuffleKind Kind, VectorType *Ty, ArrayRef<int> Mask,
566559
TTI::TargetCostKind CostKind, int Index, VectorType *SubTp,

‎llvm/lib/Analysis/TargetTransformInfo.cpp

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -862,15 +862,6 @@ InstructionCost TargetTransformInfo::getArithmeticInstrCost(
862862
return Cost;
863863
}
864864

865-
InstructionCost TargetTransformInfo::getAltInstrCost(
866-
VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
867-
const SmallBitVector &OpcodeMask, TTI::TargetCostKind CostKind) const {
868-
InstructionCost Cost =
869-
TTIImpl->getAltInstrCost(VecTy, Opcode0, Opcode1, OpcodeMask, CostKind);
870-
assert(Cost >= 0 && "TTI should not produce negative costs!");
871-
return Cost;
872-
}
873-
874865
InstructionCost TargetTransformInfo::getShuffleCost(
875866
ShuffleKind Kind, VectorType *Ty, ArrayRef<int> Mask,
876867
TTI::TargetCostKind CostKind, int Index, VectorType *SubTp,

‎llvm/lib/Target/X86/X86TargetTransformInfo.cpp

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1459,15 +1459,6 @@ InstructionCost X86TTIImpl::getArithmeticInstrCost(
14591459
Args, CxtI);
14601460
}
14611461

1462-
InstructionCost
1463-
X86TTIImpl::getAltInstrCost(VectorType *VecTy, unsigned Opcode0,
1464-
unsigned Opcode1, const SmallBitVector &OpcodeMask,
1465-
TTI::TargetCostKind CostKind) const {
1466-
if (isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask))
1467-
return TTI::TCC_Basic;
1468-
return InstructionCost::getInvalid();
1469-
}
1470-
14711462
InstructionCost X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind,
14721463
VectorType *BaseTp,
14731464
ArrayRef<int> Mask,

‎llvm/lib/Target/X86/X86TargetTransformInfo.h

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -140,11 +140,6 @@ class X86TTIImpl : public BasicTTIImplBase<X86TTIImpl> {
140140
TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None},
141141
ArrayRef<const Value *> Args = ArrayRef<const Value *>(),
142142
const Instruction *CxtI = nullptr);
143-
InstructionCost getAltInstrCost(VectorType *VecTy, unsigned Opcode0,
144-
unsigned Opcode1,
145-
const SmallBitVector &OpcodeMask,
146-
TTI::TargetCostKind CostKind) const;
147-
148143
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp,
149144
ArrayRef<int> Mask,
150145
TTI::TargetCostKind CostKind, int Index,

‎llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp

Lines changed: 0 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -8428,25 +8428,6 @@ BoUpSLP::getEntryCost(const TreeEntry *E, ArrayRef<Value *> VectorizedVals,
84288428
Mask);
84298429
VecCost += TTI->getShuffleCost(TargetTransformInfo::SK_PermuteTwoSrc,
84308430
FinalVecTy, Mask);
8431-
// Patterns like [fadd,fsub] can be combined into a single instruction
8432-
// in x86. Reordering them into [fsub,fadd] blocks this pattern. So we
8433-
// need to take into account their order when looking for the most used
8434-
// order.
8435-
unsigned Opcode0 = E->getOpcode();
8436-
unsigned Opcode1 = E->getAltOpcode();
8437-
// The opcode mask selects between the two opcodes.
8438-
SmallBitVector OpcodeMask(E->Scalars.size(), false);
8439-
for (unsigned Lane : seq<unsigned>(0, E->Scalars.size()))
8440-
if (cast<Instruction>(E->Scalars[Lane])->getOpcode() == Opcode1)
8441-
OpcodeMask.set(Lane);
8442-
// If this pattern is supported by the target then we consider the
8443-
// order.
8444-
if (TTI->isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask)) {
8445-
InstructionCost AltVecCost =
8446-
TTI->getAltInstrCost(VecTy, Opcode0, Opcode1, OpcodeMask, CostKind);
8447-
return AltVecCost < VecCost ? AltVecCost : VecCost;
8448-
}
8449-
// TODO: Check the reverse order too.
84508431
return VecCost;
84518432
};
84528433
return GetCostDiff(GetScalarCost, GetVectorCost);

‎llvm/test/Transforms/SLPVectorizer/X86/supernode.ll

Lines changed: 10 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -103,23 +103,21 @@ define void @test_supernode_addsub_alt(ptr %Aarray, ptr %Barray, ptr %Carray, pt
103103
; ENABLED-LABEL: @test_supernode_addsub_alt(
104104
; ENABLED-NEXT: entry:
105105
; ENABLED-NEXT: [[IDXA1:%.*]] = getelementptr inbounds double, ptr [[AARRAY:%.*]], i64 1
106+
; ENABLED-NEXT: [[IDXB1:%.*]] = getelementptr inbounds double, ptr [[BARRAY:%.*]], i64 1
106107
; ENABLED-NEXT: [[IDXC1:%.*]] = getelementptr inbounds double, ptr [[CARRAY:%.*]], i64 1
108+
; ENABLED-NEXT: [[IDXS1:%.*]] = getelementptr inbounds double, ptr [[SARRAY:%.*]], i64 1
107109
; ENABLED-NEXT: [[A0:%.*]] = load double, ptr [[AARRAY]], align 8
108110
; ENABLED-NEXT: [[A1:%.*]] = load double, ptr [[IDXA1]], align 8
111+
; ENABLED-NEXT: [[B0:%.*]] = load double, ptr [[BARRAY]], align 8
112+
; ENABLED-NEXT: [[B1:%.*]] = load double, ptr [[IDXB1]], align 8
109113
; ENABLED-NEXT: [[C0:%.*]] = load double, ptr [[CARRAY]], align 8
110114
; ENABLED-NEXT: [[C1:%.*]] = load double, ptr [[IDXC1]], align 8
111-
; ENABLED-NEXT: [[TMP0:%.*]] = load <2 x double>, ptr [[BARRAY:%.*]], align 8
112-
; ENABLED-NEXT: [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A0]], i32 0
113-
; ENABLED-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[C1]], i32 1
114-
; ENABLED-NEXT: [[TMP3:%.*]] = fsub fast <2 x double> [[TMP2]], [[TMP0]]
115-
; ENABLED-NEXT: [[TMP4:%.*]] = fadd fast <2 x double> [[TMP2]], [[TMP0]]
116-
; ENABLED-NEXT: [[TMP5:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> [[TMP4]], <2 x i32> <i32 0, i32 3>
117-
; ENABLED-NEXT: [[TMP6:%.*]] = insertelement <2 x double> poison, double [[C0]], i32 0
118-
; ENABLED-NEXT: [[TMP7:%.*]] = insertelement <2 x double> [[TMP6]], double [[A1]], i32 1
119-
; ENABLED-NEXT: [[TMP8:%.*]] = fsub fast <2 x double> [[TMP5]], [[TMP7]]
120-
; ENABLED-NEXT: [[TMP9:%.*]] = fadd fast <2 x double> [[TMP5]], [[TMP7]]
121-
; ENABLED-NEXT: [[TMP10:%.*]] = shufflevector <2 x double> [[TMP8]], <2 x double> [[TMP9]], <2 x i32> <i32 0, i32 3>
122-
; ENABLED-NEXT: store <2 x double> [[TMP10]], ptr [[SARRAY:%.*]], align 8
115+
; ENABLED-NEXT: [[SUBA0B0:%.*]] = fsub fast double [[A0]], [[B0]]
116+
; ENABLED-NEXT: [[ADDB1C1:%.*]] = fadd fast double [[B1]], [[C1]]
117+
; ENABLED-NEXT: [[SUB0:%.*]] = fsub fast double [[SUBA0B0]], [[C0]]
118+
; ENABLED-NEXT: [[ADD1:%.*]] = fadd fast double [[ADDB1C1]], [[A1]]
119+
; ENABLED-NEXT: store double [[SUB0]], ptr [[SARRAY]], align 8
120+
; ENABLED-NEXT: store double [[ADD1]], ptr [[IDXS1]], align 8
123121
; ENABLED-NEXT: ret void
124122
;
125123
entry:

‎llvm/test/Transforms/SLPVectorizer/X86/vectorize-widest-phis.ll

Lines changed: 9 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -12,24 +12,22 @@ define void @foo() {
1212
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> [[TMP0]], float [[CONV]], i32 1
1313
; CHECK-NEXT: br label [[BB2:%.*]]
1414
; CHECK: bb2:
15-
; CHECK-NEXT: [[TMP2:%.*]] = phi <4 x float> [ [[TMP1]], [[BB1]] ], [ [[TMP14:%.*]], [[BB3:%.*]] ]
15+
; CHECK-NEXT: [[TMP2:%.*]] = phi <4 x float> [ [[TMP1]], [[BB1]] ], [ [[TMP10:%.*]], [[BB3:%.*]] ]
1616
; CHECK-NEXT: [[TMP3:%.*]] = load double, ptr undef, align 8
1717
; CHECK-NEXT: br i1 undef, label [[BB3]], label [[BB4:%.*]]
1818
; CHECK: bb4:
1919
; CHECK-NEXT: [[TMP4:%.*]] = fpext <4 x float> [[TMP2]] to <4 x double>
2020
; CHECK-NEXT: [[CONV2:%.*]] = uitofp i16 undef to double
21-
; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x double> <double undef, double poison>, double [[TMP3]], i32 1
22-
; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x double> <double undef, double poison>, double [[CONV2]], i32 1
23-
; CHECK-NEXT: [[TMP7:%.*]] = fsub <2 x double> [[TMP5]], [[TMP6]]
24-
; CHECK-NEXT: [[TMP8:%.*]] = fadd <2 x double> [[TMP5]], [[TMP6]]
25-
; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <2 x double> [[TMP7]], <2 x double> [[TMP8]], <2 x i32> <i32 0, i32 3>
26-
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <2 x double> [[TMP9]], <2 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
27-
; CHECK-NEXT: [[TMP11:%.*]] = fcmp ogt <4 x double> [[TMP10]], [[TMP4]]
28-
; CHECK-NEXT: [[TMP12:%.*]] = fptrunc <4 x double> [[TMP10]] to <4 x float>
29-
; CHECK-NEXT: [[TMP13:%.*]] = select <4 x i1> [[TMP11]], <4 x float> [[TMP2]], <4 x float> [[TMP12]]
21+
; CHECK-NEXT: [[ADD1:%.*]] = fadd double [[TMP3]], [[CONV2]]
22+
; CHECK-NEXT: [[SUB1:%.*]] = fsub double undef, undef
23+
; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x double> <double poison, double poison, double undef, double undef>, double [[SUB1]], i32 0
24+
; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x double> [[TMP5]], double [[ADD1]], i32 1
25+
; CHECK-NEXT: [[TMP7:%.*]] = fcmp ogt <4 x double> [[TMP6]], [[TMP4]]
26+
; CHECK-NEXT: [[TMP8:%.*]] = fptrunc <4 x double> [[TMP6]] to <4 x float>
27+
; CHECK-NEXT: [[TMP9:%.*]] = select <4 x i1> [[TMP7]], <4 x float> [[TMP2]], <4 x float> [[TMP8]]
3028
; CHECK-NEXT: br label [[BB3]]
3129
; CHECK: bb3:
32-
; CHECK-NEXT: [[TMP14]] = phi <4 x float> [ [[TMP13]], [[BB4]] ], [ [[TMP2]], [[BB2]] ]
30+
; CHECK-NEXT: [[TMP10]] = phi <4 x float> [ [[TMP9]], [[BB4]] ], [ [[TMP2]], [[BB2]] ]
3331
; CHECK-NEXT: br label [[BB2]]
3432
;
3533
entry:

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