Skip to content

Commit fbb8b41

Browse files
tstellartstellar
committed
Revert "[AArch64][GlobalISel] Legalize bswap <2 x i16>"
This reverts commit 5cd63e9. https://bugs.llvm.org/show_bug.cgi?id=51707
1 parent 1c198b3 commit fbb8b41

File tree

4 files changed

+3
-87
lines changed

4 files changed

+3
-87
lines changed

‎llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

Lines changed: 1 addition & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -103,8 +103,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
103103
getActionDefinitionsBuilder(G_BSWAP)
104104
.legalFor({s32, s64, v4s32, v2s32, v2s64})
105105
.clampScalar(0, s32, s64)
106-
.widenScalarToNextPow2(0)
107-
.customIf(typeIs(0, v2s16)); // custom lower as G_REV32 + G_LSHR
106+
.widenScalarToNextPow2(0);
108107

109108
getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR})
110109
.legalFor({s32, s64, v2s32, v4s32, v4s16, v8s16, v16s8, v8s8})
@@ -799,8 +798,6 @@ bool AArch64LegalizerInfo::legalizeCustom(LegalizerHelper &Helper,
799798
case TargetOpcode::G_LOAD:
800799
case TargetOpcode::G_STORE:
801800
return legalizeLoadStore(MI, MRI, MIRBuilder, Observer);
802-
case TargetOpcode::G_BSWAP:
803-
return legalizeBSwap(MI, MRI, MIRBuilder);
804801
case TargetOpcode::G_SHL:
805802
case TargetOpcode::G_ASHR:
806803
case TargetOpcode::G_LSHR:
@@ -1015,46 +1012,6 @@ bool AArch64LegalizerInfo::legalizeLoadStore(
10151012
return true;
10161013
}
10171014

1018-
bool AArch64LegalizerInfo::legalizeBSwap(MachineInstr &MI,
1019-
MachineRegisterInfo &MRI,
1020-
MachineIRBuilder &MIRBuilder) const {
1021-
assert(MI.getOpcode() == TargetOpcode::G_BSWAP);
1022-
1023-
// The <2 x half> case needs special lowering because there isn't an
1024-
// instruction that does that directly. Instead, we widen to <8 x i8>
1025-
// and emit a G_REV32 followed by a G_LSHR knowing that instruction selection
1026-
// will later match them as:
1027-
//
1028-
// rev32.8b v0, v0
1029-
// ushr.2s v0, v0, #16
1030-
//
1031-
// We could emit those here directly, but it seems better to keep things as
1032-
// generic as possible through legalization, and avoid committing layering
1033-
// violations by legalizing & selecting here at the same time.
1034-
1035-
Register ValReg = MI.getOperand(1).getReg();
1036-
assert(LLT::fixed_vector(2, 16) == MRI.getType(ValReg));
1037-
const LLT v2s32 = LLT::fixed_vector(2, 32);
1038-
const LLT v8s8 = LLT::fixed_vector(8, 8);
1039-
const LLT s32 = LLT::scalar(32);
1040-
1041-
auto Undef = MIRBuilder.buildUndef(v8s8);
1042-
auto Insert =
1043-
MIRBuilder
1044-
.buildInstr(TargetOpcode::INSERT_SUBREG, {v8s8}, {Undef, ValReg})
1045-
.addImm(AArch64::ssub);
1046-
auto Rev32 = MIRBuilder.buildInstr(AArch64::G_REV32, {v8s8}, {Insert});
1047-
auto Bitcast = MIRBuilder.buildBitcast(v2s32, Rev32);
1048-
auto Amt = MIRBuilder.buildConstant(v2s32, 16);
1049-
auto UShr =
1050-
MIRBuilder.buildInstr(TargetOpcode::G_LSHR, {v2s32}, {Bitcast, Amt});
1051-
auto Zero = MIRBuilder.buildConstant(s32, 0);
1052-
auto Extract = MIRBuilder.buildExtractVectorElement(s32, UShr, Zero);
1053-
MIRBuilder.buildBitcast({MI.getOperand(0).getReg()}, Extract);
1054-
MI.eraseFromParent();
1055-
return true;
1056-
}
1057-
10581015
bool AArch64LegalizerInfo::legalizeVaArg(MachineInstr &MI,
10591016
MachineRegisterInfo &MRI,
10601017
MachineIRBuilder &MIRBuilder) const {

‎llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -35,8 +35,6 @@ class AArch64LegalizerInfo : public LegalizerInfo {
3535
MachineInstr &MI) const override;
3636

3737
private:
38-
bool legalizeBSwap(MachineInstr &MI, MachineRegisterInfo &MRI,
39-
MachineIRBuilder &MIRBuilder) const;
4038
bool legalizeVaArg(MachineInstr &MI, MachineRegisterInfo &MRI,
4139
MachineIRBuilder &MIRBuilder) const;
4240
bool legalizeLoadStore(MachineInstr &MI, MachineRegisterInfo &MRI,

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir

Lines changed: 0 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -8,8 +8,6 @@
88

99
define i16 @bswap_s16(i16 %a) { ret i16 0 }
1010

11-
define <2 x i16> @bswap_2xi16(<2 x i16> %a) { ret <2 x i16> <i16 0, i16 0> }
12-
1311
attributes #0 = { nounwind readnone speculatable willreturn }
1412

1513
...
@@ -44,40 +42,3 @@ body: |
4442
RET_ReallyLR implicit $w0
4543
4644
...
47-
---
48-
name: bswap_2xi16
49-
alignment: 4
50-
tracksRegLiveness: true
51-
registers:
52-
- { id: 0, class: _ }
53-
- { id: 1, class: _ }
54-
liveins:
55-
- { reg: '$s0' }
56-
frameInfo:
57-
maxAlignment: 1
58-
machineFunctionInfo: {}
59-
body: |
60-
bb.1:
61-
liveins: $s0
62-
63-
; CHECK-LABEL: name: bswap_2xi16
64-
; CHECK: liveins: $s0
65-
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $s0
66-
; CHECK: [[DEF:%[0-9]+]]:_(<8 x s8>) = G_IMPLICIT_DEF
67-
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:_(<8 x s8>) = INSERT_SUBREG [[DEF]](<8 x s8>), [[COPY]](<2 x s16>), %subreg.ssub
68-
; CHECK: [[REV32_:%[0-9]+]]:_(<8 x s8>) = G_REV32 [[INSERT_SUBREG]]
69-
; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s32>) = G_BITCAST [[REV32_]](<8 x s8>)
70-
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
71-
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
72-
; CHECK: [[LSHR:%[0-9]+]]:_(<2 x s32>) = G_LSHR [[BITCAST]], [[BUILD_VECTOR]](<2 x s32>)
73-
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
74-
; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[LSHR]](<2 x s32>), [[C1]](s64)
75-
; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[EVEC]](s32)
76-
; CHECK: $s0 = COPY [[BITCAST1]](<2 x s16>)
77-
; CHECK: RET_ReallyLR
78-
%0:_(<2 x s16>) = COPY $s0
79-
%1:_(<2 x s16>) = G_BSWAP %0
80-
$s0 = COPY %1(<2 x s16>)
81-
RET_ReallyLR
82-
83-
...

‎llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -555,8 +555,8 @@
555555
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
556556
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
557557
# DEBUG-NEXT: G_BSWAP (opcode {{[0-9]+}}): 1 type index, 0 imm indices
558-
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
559-
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
558+
# DEBUG-NEXT: .. the first uncovered type index: 1, OK
559+
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
560560
# DEBUG-NEXT: G_BITREVERSE (opcode {{[0-9]+}}): 1 type index, 0 imm indices
561561
# DEBUG-NEXT: .. the first uncovered type index: 1, OK
562562
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK

0 commit comments

Comments
 (0)