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llvm: fix few typos in filecheck tests
and few more
1 parent bf4d99e commit fbc3212

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23 files changed

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-50
lines changed

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-50
lines changed

‎llvm/test/Analysis/CostModel/AArch64/sve-shuffle-broadcast.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@ define void @broadcast() #0{
3131
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %22 = shufflevector <vscale x 8 x i1> undef, <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer
3232
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %23 = shufflevector <vscale x 4 x i1> undef, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
3333
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %24 = shufflevector <vscale x 2 x i1> undef, <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer
34-
; CHECK-NETX: Cost Model: Found an estimated cost of 0 for instruction: ret void
34+
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
3535

3636
%zero = shufflevector <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
3737
%1 = shufflevector <vscale x 32 x i8> undef, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer

‎llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/diverged-entry-headers.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -90,7 +90,7 @@ S:
9090
br i1 %cond.uni, label %exit, label %T
9191

9292
T:
93-
; CHECK-NIT: DIVERGENT: %tt.phi = phi i32
93+
; CHECK-NOT: DIVERGENT: %tt.phi = phi i32
9494
%tt.phi = phi i32 [ %ss, %S ], [ %a, %entry ]
9595
%tt = add i32 %b, 1
9696
br label %P

‎llvm/test/CodeGen/AArch64/arm64_32-atomics.ll

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -2,70 +2,70 @@
22
; RUN: llc -mtriple=arm64_32-apple-ios7.0 -mattr=+outline-atomics -o - %s | FileCheck %s -check-prefix=OUTLINE-ATOMICS
33

44
define i8 @test_load_8(ptr %addr) {
5-
; CHECK-LABAL: test_load_8:
5+
; CHECK-LABEL: test_load_8:
66
; CHECK: ldarb w0, [x0]
77
%val = load atomic i8, ptr %addr seq_cst, align 1
88
ret i8 %val
99
}
1010

1111
define i16 @test_load_16(ptr %addr) {
12-
; CHECK-LABAL: test_load_16:
12+
; CHECK-LABEL: test_load_16:
1313
; CHECK: ldarh w0, [x0]
1414
%val = load atomic i16, ptr %addr acquire, align 2
1515
ret i16 %val
1616
}
1717

1818
define i32 @test_load_32(ptr %addr) {
19-
; CHECK-LABAL: test_load_32:
19+
; CHECK-LABEL: test_load_32:
2020
; CHECK: ldar w0, [x0]
2121
%val = load atomic i32, ptr %addr seq_cst, align 4
2222
ret i32 %val
2323
}
2424

2525
define i64 @test_load_64(ptr %addr) {
26-
; CHECK-LABAL: test_load_64:
26+
; CHECK-LABEL: test_load_64:
2727
; CHECK: ldar x0, [x0]
2828
%val = load atomic i64, ptr %addr seq_cst, align 8
2929
ret i64 %val
3030
}
3131

3232
define ptr @test_load_ptr(ptr %addr) {
33-
; CHECK-LABAL: test_load_ptr:
33+
; CHECK-LABEL: test_load_ptr:
3434
; CHECK: ldar w0, [x0]
3535
%val = load atomic ptr, ptr %addr seq_cst, align 8
3636
ret ptr %val
3737
}
3838

3939
define void @test_store_8(ptr %addr) {
40-
; CHECK-LABAL: test_store_8:
40+
; CHECK-LABEL: test_store_8:
4141
; CHECK: stlrb wzr, [x0]
4242
store atomic i8 0, ptr %addr seq_cst, align 1
4343
ret void
4444
}
4545

4646
define void @test_store_16(ptr %addr) {
47-
; CHECK-LABAL: test_store_16:
47+
; CHECK-LABEL: test_store_16:
4848
; CHECK: stlrh wzr, [x0]
4949
store atomic i16 0, ptr %addr seq_cst, align 2
5050
ret void
5151
}
5252

5353
define void @test_store_32(ptr %addr) {
54-
; CHECK-LABAL: test_store_32:
54+
; CHECK-LABEL: test_store_32:
5555
; CHECK: stlr wzr, [x0]
5656
store atomic i32 0, ptr %addr seq_cst, align 4
5757
ret void
5858
}
5959

6060
define void @test_store_64(ptr %addr) {
61-
; CHECK-LABAL: test_store_64:
61+
; CHECK-LABEL: test_store_64:
6262
; CHECK: stlr xzr, [x0]
6363
store atomic i64 0, ptr %addr seq_cst, align 8
6464
ret void
6565
}
6666

6767
define void @test_store_ptr(ptr %addr) {
68-
; CHECK-LABAL: test_store_ptr:
68+
; CHECK-LABEL: test_store_ptr:
6969
; CHECK: stlr wzr, [x0]
7070
store atomic ptr null, ptr %addr seq_cst, align 8
7171
ret void

‎llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-diff-scope-same-key.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,7 @@ define void @a() "sign-return-address"="all" {
2828
}
2929

3030
define void @b() "sign-return-address"="non-leaf" {
31-
; CHECK-LABE: b: // @b
31+
; CHECK-LABEL: b: // @b
3232
; V8A-NOT: hint #25
3333
; V83A-NOT: paciasp
3434
; CHECK-NOT: .cfi_negate_ra_state

‎llvm/test/CodeGen/AArch64/stp-opt-with-renaming-undef-assert.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212

1313
# This test also checks that pairwise store STP is generated.
1414

15-
# CHECK-LABLE: test
15+
# CHECK-LABEL: test
1616
# CHECK: bb.0:
1717
# CHECK-NEXT: liveins: $x0, $x17, $x18
1818
# CHECK: renamable $q13_q14_q15 = LD3Threev16b undef renamable $x17 :: (load (s384) from `ptr undef`, align 64)

‎llvm/test/CodeGen/AMDGPU/addrspacecast.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -108,7 +108,7 @@ define amdgpu_kernel void @use_global_to_flat_addrspacecast(ptr addrspace(1) %pt
108108
}
109109

110110
; no-op
111-
; HSA-LABEl: {{^}}use_constant_to_flat_addrspacecast:
111+
; HSA-LABEL: {{^}}use_constant_to_flat_addrspacecast:
112112
; HSA: s_load_dwordx2 s[[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]]
113113
; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]]
114114
; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]]
@@ -119,7 +119,7 @@ define amdgpu_kernel void @use_constant_to_flat_addrspacecast(ptr addrspace(4) %
119119
ret void
120120
}
121121

122-
; HSA-LABEl: {{^}}use_constant_to_global_addrspacecast:
122+
; HSA-LABEL: {{^}}use_constant_to_global_addrspacecast:
123123
; HSA: s_load_dwordx2 s[[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]]
124124
; CI-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]]
125125
; CI-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]]

‎llvm/test/CodeGen/ARM/dsp-loop-indexing.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@
2222
; CHECK-DEFAULT: ldr{{.*}}, #4]
2323
; CHECK-DEFAULT: str{{.*}}, #4]
2424
; CHECK-DEFAULT: ldr{{.*}}, #8]!
25-
; CHECK-DEAFULT: ldr{{.*}}, #8]!
25+
; CHECK-DEFAULT: ldr{{.*}}, #8]!
2626
; CHECK-DEFAULT: str{{.*}}, #8]!
2727

2828
; CHECK-COMPLEX: ldr{{.*}}, #8]!

‎llvm/test/CodeGen/Mips/optimizeAndPlusShift.ll

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -3,11 +3,11 @@
33
; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnuabi64 | FileCheck %s --check-prefixes=MIPS64
44

55
define i32 @shl_32(i32 %a, i32 %b) {
6-
; MIPS32-LABLE: shl_32:
6+
; MIPS32-LABEL: shl_32:
77
; MIPS32: # %bb.0:
88
; MIPS32-NEXT: jr $ra
99
; MIPS32-NEXT: sllv $2, $4, $5
10-
; MIPS64-LABLE: shl_32:
10+
; MIPS64-LABEL: shl_32:
1111
; MIPS64: # %bb.0:
1212
; MIPS64-NEXT: sll $1, $5, 0
1313
; MIPS64-NEXT: sll $2, $4, 0
@@ -19,11 +19,11 @@ define i32 @shl_32(i32 %a, i32 %b) {
1919
}
2020

2121
define i32 @lshr_32(i32 %a, i32 %b) {
22-
; MIPS32-LABLE: lshr_32:
22+
; MIPS32-LABEL: lshr_32:
2323
; MIPS32: # %bb.0:
2424
; MIPS32-NEXT: jr $ra
2525
; MIPS32-NEXT: srlv $2, $4, $5
26-
; MIPS64-LABLE: lshr_32:
26+
; MIPS64-LABEL: lshr_32:
2727
; MIPS64: # %bb.0:
2828
; MIPS64-NEXT: sll $1, $5, 0
2929
; MIPS64-NEXT: sll $2, $4, 0
@@ -35,11 +35,11 @@ define i32 @lshr_32(i32 %a, i32 %b) {
3535
}
3636

3737
define i32 @ashr_32(i32 %a, i32 %b) {
38-
; MIPS32-LABLE: ashr_32:
38+
; MIPS32-LABEL: ashr_32:
3939
; MIPS32: # %bb.0:
4040
; MIPS32-NEXT: jr $ra
4141
; MIPS32-NEXT: srav $2, $4, $5
42-
; MIPS64-LABLE: ashr_32:
42+
; MIPS64-LABEL: ashr_32:
4343
; MIPS64: # %bb.0:
4444
; MIPS64-NEXT: sll $1, $5, 0
4545
; MIPS64-NEXT: sll $2, $4, 0
@@ -51,7 +51,7 @@ define i32 @ashr_32(i32 %a, i32 %b) {
5151
}
5252

5353
define i64 @shl_64(i64 %a, i64 %b) {
54-
; MIPS64-LABLE: shl_64:
54+
; MIPS64-LABEL: shl_64:
5555
; MIPS64: # %bb.0:
5656
; MIPS64-NEXT: sll $1, $5, 0
5757
; MIPS64-NEXT: jr $ra
@@ -62,7 +62,7 @@ define i64 @shl_64(i64 %a, i64 %b) {
6262
}
6363

6464
define i64 @lshr_64(i64 %a, i64 %b) {
65-
; MIPS64-LABLE: lshr_64:
65+
; MIPS64-LABEL: lshr_64:
6666
; MIPS64: # %bb.0:
6767
; MIPS64-NEXT: sll $1, $5, 0
6868
; MIPS64-NEXT: jr $ra
@@ -73,7 +73,7 @@ define i64 @lshr_64(i64 %a, i64 %b) {
7373
}
7474

7575
define i64 @ashr_64(i64 %a, i64 %b) {
76-
; MIPS64-LABLE: ashr_64:
76+
; MIPS64-LABEL: ashr_64:
7777
; MIPS64: # %bb.0:
7878
; MIPS64-NEXT: sll $1, $5, 0
7979
; MIPS64-NEXT: jr $ra

‎llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_usm_storage_classes/intel-usm-addrspaces.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@
66
; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
77

88
; CHECK-: Capability USMStorageClassesINTEL
9-
; CHECK-SPIRV-WITHOUT-NO: Capability USMStorageClassesINTEL
9+
; CHECK-SPIRV-WITHOUT-NOT: Capability USMStorageClassesINTEL
1010
; CHECK-SPIRV-EXT-DAG: %[[DevTy:[0-9]+]] = OpTypePointer DeviceOnlyINTEL %[[#]]
1111
; CHECK-SPIRV-EXT-DAG: %[[HostTy:[0-9]+]] = OpTypePointer HostOnlyINTEL %[[#]]
1212
; CHECK-SPIRV-DAG: %[[CrsWrkTy:[0-9]+]] = OpTypePointer CrossWorkgroup %[[#]]

‎llvm/test/CodeGen/SystemZ/prefetch-04.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@
66
;
77
; CHECK-LABEL: for.body
88
; CHECK: call void @llvm.prefetch.p0(ptr %scevgep, i32 1, i32 3, i32 1
9-
; CHECK-not: call void @llvm.prefetch
9+
; CHECK-NOT: call void @llvm.prefetch
1010

1111
define void @fun(ptr nocapture %Src, ptr nocapture readonly %Dst) {
1212
entry:

‎llvm/test/CodeGen/X86/global-sections.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -36,8 +36,8 @@ bb5:
3636
}
3737

3838
; LINUX: .size F2,
39-
; LINUX-NEX: .cfi_endproc
40-
; LINUX-NEX: .section .rodata,"a",@progbits
39+
; LINUX-NEXT: .cfi_endproc
40+
; LINUX-NEXT: .section .rodata,"a",@progbits
4141

4242
; LINUX-SECTIONS: .section .text.F2,"ax",@progbits
4343
; LINUX-SECTIONS: .size F2,

‎llvm/test/CodeGen/X86/tailregccpic.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -13,12 +13,12 @@ entry:
1313
ret void
1414
}
1515

16-
;CHECK-LABLE: tail_call_regcall:
16+
;CHECK-LABEL: tail_call_regcall:
1717
;CHECK: # %bb.0:
1818
;CHECK-NEXT: jmp __regcall3__func # TAILCALL
1919
;CHECK-NEXT: .Lfunc_end0:
2020

21-
;CHECK-LABLE: __regcall3__func:
21+
;CHECK-LABEL: __regcall3__func:
2222
;CHECK: addl $_GLOBAL_OFFSET_TABLE_+({{.*}}), %ecx
2323
;CHECK-NEXT: movl a0@GOT(%ecx), %ecx
2424
;CHECK-NEXT: movl %eax, (%ecx)

‎llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -43,7 +43,7 @@ debugValueSubstitutions:
4343
body: |
4444
bb.0.entry:
4545
successors: %bb.1, %bb.2
46-
; CHECK-LABE: bb.0.entry:
46+
; CHECK-LABEL: bb.0.entry:
4747
4848
$rax = MOV64ri 1, debug-instr-number 1, debug-location !17
4949
DBG_INSTR_REF !16, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0), debug-location !17
@@ -69,8 +69,8 @@ body: |
6969
;KILL implicit killed $eflags, debug-instr-number 4, debug-location !17
7070
;DBG_INSTR_REF !16, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(4, 0), debug-location !17
7171
;;; Test non-def operand
72-
;; check: DBG_INSTR_REF {{.+}}, dbg-instr-ref(4, 0)
73-
;; check-next: DBG_VALUE_LIST {{.+}}, $noreg
72+
;; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(4, 0)
73+
;; CHECK-NEXT: DBG_VALUE_LIST {{.+}}, $noreg
7474
7575
$noreg = MOV32ri 1, debug-instr-number 5, debug-location !17
7676
DBG_INSTR_REF !16, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(5, 0), debug-location !17

‎llvm/test/MC/ARM/coff-relocations.s

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,7 @@ branch24t_1:
2525
bl target
2626

2727
@ CHECK-ENCODING-LABEL: <branch24t_1>:
28-
@ CHECK-ENCODING-NEXR: bl {{.+}} @ imm = #0
28+
@ CHECK-ENCODING-NEXT: bl {{.+}} @ imm = #0
2929

3030
.thumb_func
3131
branch20t:

‎llvm/test/MC/Mips/expansion-jal-sym-pic.s

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -227,12 +227,12 @@ local_label:
227227
# XO32-NEXT: .reloc ($tmp1), R_MIPS_JALR, weak_label
228228

229229
# ELF-XO32: 3c 19 00 00 lui $25, 0
230-
# ELF-XO32-MEXT: R_MIPS_CALL_HI16 weak_label
231-
# ELF-XO32-MEXT: 03 3c c8 21 addu $25, $25, $gp
232-
# ELF-XO32-MEXT: 8f 39 00 00 lw $25, 0($25)
233-
# ELF-XO32-MEXT: R_MIPS_CALL_LO16 weak_label
234-
# ELF-XO32-MEXT: 03 20 f8 09 jalr $25
235-
# ELF-XO32-MEXT: R_MIPS_JALR weak_label
230+
# ELF-XO32-NEXT: R_MIPS_CALL_HI16 weak_label
231+
# ELF-XO32-NEXT: 03 3c c8 21 addu $25, $25, $gp
232+
# ELF-XO32-NEXT: 8f 39 00 00 lw $25, 0($25)
233+
# ELF-XO32-NEXT: R_MIPS_CALL_LO16 weak_label
234+
# ELF-XO32-NEXT: 03 20 f8 09 jalr $25
235+
# ELF-XO32-NEXT: R_MIPS_JALR weak_label
236236

237237
# N32: lw $25, %call16(weak_label)($gp) # encoding: [0x8f,0x99,A,A]
238238
# N32: # fixup A - offset: 0, value: %call16(weak_label), kind: fixup_Mips_CALL16

‎llvm/test/Transforms/Inline/update_invoke_prof.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -66,7 +66,7 @@ ret:
6666
; CHECK: invoke void @callee2(
6767
; CHECK-NEXT: {{.*}} !prof ![[PROF3:[0-9]+]]
6868

69-
; CHECK-LABL: @callee(
69+
; CHECK-LABEL: @callee(
7070
; CHECK: invoke void %func(
7171
; CHECK-NEXT: {{.*}} !prof ![[PROF4:[0-9]+]]
7272
; CHECK: invoke void @callee1(

‎llvm/test/Transforms/InstCombine/lifetime-sanitizer.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -56,7 +56,7 @@ entry:
5656

5757
call void @llvm.lifetime.start.p0(i64 1, ptr %text)
5858
call void @llvm.lifetime.end.p0(i64 1, ptr %text)
59-
; CHECK-NO: call void @llvm.lifetime
59+
; CHECK-NOT: call void @llvm.lifetime
6060

6161
call void @foo(ptr %text) ; Keep alloca alive
6262

‎llvm/test/Transforms/LoopUnroll/peel-loop2.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@ for.end:
3232
ret void
3333
}
3434

35-
; CHECK_LABEL: @funca
35+
; CHECK-LABEL: @funca
3636

3737
; Peeled iteration
3838
; CHECK: %[[REG1:[0-9]+]] = load i8, ptr @Comma

‎llvm/test/Transforms/LoopVectorize/memdep.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -244,7 +244,7 @@ for.end:
244244
; RIGHTVF-LABEL: @pr34283
245245
; RIGHTVF: <4 x i64>
246246

247-
; WRONGVF-LABLE: @pr34283
247+
; WRONGVF-LABEL: @pr34283
248248
; WRONGVF-NOT: <8 x i64>
249249

250250
@a = common local_unnamed_addr global [64 x i32] zeroinitializer, align 16

‎llvm/test/Transforms/LoopVersioning/wrapping-pointer-non-integral-addrspace.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128-ni:10:11:12:13"
1313
declare i64 @julia_steprange_last_4949()
1414

1515
define void @"japi1_align!_9477"(ptr %arg) {
16-
; LV-LAVEL: L26.lver.check
16+
; LV-LABEL: L26.lver.check
1717
; LV: [[OFMul:%[^ ]*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 4, i64 [[Step:%[^ ]*]])
1818
; LV-NEXT: [[OFMulResult:%[^ ]*]] = extractvalue { i64, i1 } [[OFMul]], 0
1919
; LV-NEXT: [[OFMulOverflow:%[^ ]*]] = extractvalue { i64, i1 } [[OFMul]], 1

‎llvm/test/Transforms/PartiallyInlineLibCalls/X86/good-prototype.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@ entry:
2121

2222
define float @f_writeonly(float %val) {
2323
; CHECK-LABEL: @f_writeonly(
24-
; CHECK-NEXt: [[RES:%.*]] = tail call float @sqrtf(float [[VAL:%.*]]) #[[READNONE]]
24+
; CHECK-NEXT: [[RES:%.*]] = tail call float @sqrtf(float [[VAL:%.*]]) #[[READNONE]]
2525
%res = tail call float @sqrtf(float %val) writeonly
2626
ret float %res
2727
}

‎llvm/test/Verifier/AMDGPU/intrinsic-immarg.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -670,7 +670,7 @@ declare void @llvm.amdgcn.buffer.atomic.fadd.f32(float, <4 x i32>, i32, i32, i1)
670670
define amdgpu_cs void @test_buffer_atomic_fadd(float %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %offset, i1 %slc) {
671671
; CHECK: immarg operand has non-immediate parameter
672672
; CHECK-NEXT: i1 %slc
673-
; CHECK-ENXT: call void @llvm.amdgcn.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %offset, i1 %slc)
673+
; CHECK-NEXT: call void @llvm.amdgcn.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %offset, i1 %slc)
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call void @llvm.amdgcn.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %offset, i1 %slc)
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ret void
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}

‎llvm/test/tools/llvm-ar/replace-update.test

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@@ -57,7 +57,7 @@
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# MULTIPLE-SYM: symbolnew1
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# MULTIPLE-SYM-NEXT: symbol2
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# MULTIPLE-SYM-NEXTs: symbolnew3
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# MULTIPLE-SYM-NEXT: symbolnew3
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## Replace newer members with multiple older files:
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# RUN: llvm-ar ruU %t/multiple.a %t/1.o %t/2.o

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