@@ -397,6 +397,17 @@ static std::optional<unsigned> getInsertIndex(const Value *InsertInst,
397
397
return Index;
398
398
}
399
399
400
+ /// \returns a bitset for selecting opcodes. false for Opcode0 and true for
401
+ /// Opcode1.
402
+ SmallBitVector getAltInstrMask(ArrayRef<Value *> VL, unsigned Opcode0,
403
+ unsigned Opcode1) {
404
+ SmallBitVector OpcodeMask(VL.size(), false);
405
+ for (unsigned Lane : seq<unsigned>(0, VL.size()))
406
+ if (cast<Instruction>(VL[Lane])->getOpcode() == Opcode1)
407
+ OpcodeMask.set(Lane);
408
+ return OpcodeMask;
409
+ }
410
+
400
411
namespace {
401
412
/// Specifies the way the mask should be analyzed for undefs/poisonous elements
402
413
/// in the shuffle mask.
@@ -5093,11 +5104,7 @@ void BoUpSLP::reorderTopToBottom() {
5093
5104
FixedVectorType::get(TE->Scalars[0]->getType(), TE->Scalars.size());
5094
5105
unsigned Opcode0 = TE->getOpcode();
5095
5106
unsigned Opcode1 = TE->getAltOpcode();
5096
- // The opcode mask selects between the two opcodes.
5097
- SmallBitVector OpcodeMask(TE->Scalars.size(), false);
5098
- for (unsigned Lane : seq<unsigned>(0, TE->Scalars.size()))
5099
- if (cast<Instruction>(TE->Scalars[Lane])->getOpcode() == Opcode1)
5100
- OpcodeMask.set(Lane);
5107
+ SmallBitVector OpcodeMask(getAltInstrMask(TE->Scalars, Opcode0, Opcode1));
5101
5108
// If this pattern is supported by the target then we consider the order.
5102
5109
if (TTIRef.isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask)) {
5103
5110
VFToOrderedEntries[TE->getVectorFactor()].insert(TE.get());
@@ -6009,11 +6016,7 @@ bool BoUpSLP::areAltOperandsProfitable(const InstructionsState &S,
6009
6016
ArrayRef<Value *> VL) const {
6010
6017
unsigned Opcode0 = S.getOpcode();
6011
6018
unsigned Opcode1 = S.getAltOpcode();
6012
- // The opcode mask selects between the two opcodes.
6013
- SmallBitVector OpcodeMask(VL.size(), false);
6014
- for (unsigned Lane : seq<unsigned>(0, VL.size()))
6015
- if (cast<Instruction>(VL[Lane])->getOpcode() == Opcode1)
6016
- OpcodeMask.set(Lane);
6019
+ SmallBitVector OpcodeMask(getAltInstrMask(VL, Opcode0, Opcode1));
6017
6020
// If this pattern is supported by the target then consider it profitable.
6018
6021
if (TTI->isLegalAltInstr(FixedVectorType::get(S.MainOp->getType(), VL.size()),
6019
6022
Opcode0, Opcode1, OpcodeMask))
@@ -9746,11 +9749,7 @@ BoUpSLP::getEntryCost(const TreeEntry *E, ArrayRef<Value *> VectorizedVals,
9746
9749
// order.
9747
9750
unsigned Opcode0 = E->getOpcode();
9748
9751
unsigned Opcode1 = E->getAltOpcode();
9749
- // The opcode mask selects between the two opcodes.
9750
- SmallBitVector OpcodeMask(E->Scalars.size(), false);
9751
- for (unsigned Lane : seq<unsigned>(0, E->Scalars.size()))
9752
- if (cast<Instruction>(E->Scalars[Lane])->getOpcode() == Opcode1)
9753
- OpcodeMask.set(Lane);
9752
+ SmallBitVector OpcodeMask(getAltInstrMask(E->Scalars, Opcode0, Opcode1));
9754
9753
// If this pattern is supported by the target then we consider the
9755
9754
// order.
9756
9755
if (TTIRef.isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask)) {
0 commit comments