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[SLP] NFC. Refactor and add getAltInstrMask help function.
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llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp

Lines changed: 14 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -397,6 +397,17 @@ static std::optional<unsigned> getInsertIndex(const Value *InsertInst,
397397
return Index;
398398
}
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400+
/// \returns a bitset for selecting opcodes. false for Opcode0 and true for
401+
/// Opcode1.
402+
SmallBitVector getAltInstrMask(ArrayRef<Value *> VL, unsigned Opcode0,
403+
unsigned Opcode1) {
404+
SmallBitVector OpcodeMask(VL.size(), false);
405+
for (unsigned Lane : seq<unsigned>(0, VL.size()))
406+
if (cast<Instruction>(VL[Lane])->getOpcode() == Opcode1)
407+
OpcodeMask.set(Lane);
408+
return OpcodeMask;
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}
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400411
namespace {
401412
/// Specifies the way the mask should be analyzed for undefs/poisonous elements
402413
/// in the shuffle mask.
@@ -5093,11 +5104,7 @@ void BoUpSLP::reorderTopToBottom() {
50935104
FixedVectorType::get(TE->Scalars[0]->getType(), TE->Scalars.size());
50945105
unsigned Opcode0 = TE->getOpcode();
50955106
unsigned Opcode1 = TE->getAltOpcode();
5096-
// The opcode mask selects between the two opcodes.
5097-
SmallBitVector OpcodeMask(TE->Scalars.size(), false);
5098-
for (unsigned Lane : seq<unsigned>(0, TE->Scalars.size()))
5099-
if (cast<Instruction>(TE->Scalars[Lane])->getOpcode() == Opcode1)
5100-
OpcodeMask.set(Lane);
5107+
SmallBitVector OpcodeMask(getAltInstrMask(TE->Scalars, Opcode0, Opcode1));
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// If this pattern is supported by the target then we consider the order.
51025109
if (TTIRef.isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask)) {
51035110
VFToOrderedEntries[TE->getVectorFactor()].insert(TE.get());
@@ -6009,11 +6016,7 @@ bool BoUpSLP::areAltOperandsProfitable(const InstructionsState &S,
60096016
ArrayRef<Value *> VL) const {
60106017
unsigned Opcode0 = S.getOpcode();
60116018
unsigned Opcode1 = S.getAltOpcode();
6012-
// The opcode mask selects between the two opcodes.
6013-
SmallBitVector OpcodeMask(VL.size(), false);
6014-
for (unsigned Lane : seq<unsigned>(0, VL.size()))
6015-
if (cast<Instruction>(VL[Lane])->getOpcode() == Opcode1)
6016-
OpcodeMask.set(Lane);
6019+
SmallBitVector OpcodeMask(getAltInstrMask(VL, Opcode0, Opcode1));
60176020
// If this pattern is supported by the target then consider it profitable.
60186021
if (TTI->isLegalAltInstr(FixedVectorType::get(S.MainOp->getType(), VL.size()),
60196022
Opcode0, Opcode1, OpcodeMask))
@@ -9746,11 +9749,7 @@ BoUpSLP::getEntryCost(const TreeEntry *E, ArrayRef<Value *> VectorizedVals,
97469749
// order.
97479750
unsigned Opcode0 = E->getOpcode();
97489751
unsigned Opcode1 = E->getAltOpcode();
9749-
// The opcode mask selects between the two opcodes.
9750-
SmallBitVector OpcodeMask(E->Scalars.size(), false);
9751-
for (unsigned Lane : seq<unsigned>(0, E->Scalars.size()))
9752-
if (cast<Instruction>(E->Scalars[Lane])->getOpcode() == Opcode1)
9753-
OpcodeMask.set(Lane);
9752+
SmallBitVector OpcodeMask(getAltInstrMask(E->Scalars, Opcode0, Opcode1));
97549753
// If this pattern is supported by the target then we consider the
97559754
// order.
97569755
if (TTIRef.isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask)) {

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