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[RISCV] Add tests for pseudos that shouldn't have vmerge folded into them. NFC
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‎llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll

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@@ -992,6 +992,104 @@ entry:
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ret <vscale x 1 x i16> %1
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}
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; Test reductions don't have a vmerge folded into them, since the mask affects
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; the result.
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declare <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv2i32(
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<vscale x 2 x i32>,
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<vscale x 2 x i32>,
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<vscale x 2 x i32>,
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i64)
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define <vscale x 2 x i32> @vredsum(<vscale x 2 x i32> %passthru, <vscale x 2 x i32> %x, <vscale x 2 x i32> %y, <vscale x 2 x i1> %m, i64 %vl) {
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; CHECK-LABEL: vredsum:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
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; CHECK-NEXT: vmv1r.v v11, v8
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; CHECK-NEXT: vredsum.vs v11, v9, v10
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; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, ma
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; CHECK-NEXT: vmerge.vvm v8, v8, v11, v0
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; CHECK-NEXT: ret
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%a = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv2i32(
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<vscale x 2 x i32> %passthru,
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<vscale x 2 x i32> %x,
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<vscale x 2 x i32> %y,
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i64 %vl)
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%b = call <vscale x 2 x i32> @llvm.riscv.vmerge.nxv2i32.nxv2i32(<vscale x 2 x i32> %passthru, <vscale x 2 x i32> %passthru, <vscale x 2 x i32> %a, <vscale x 2 x i1> %m, i64 %vl)
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ret <vscale x 2 x i32> %b
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}
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declare <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv2f32(
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<vscale x 2 x float>,
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<vscale x 2 x float>,
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<vscale x 2 x float>,
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i64, i64)
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define <vscale x 2 x float> @vfredusum(<vscale x 2 x float> %passthru, <vscale x 2 x float> %x, <vscale x 2 x float> %y, <vscale x 2 x i1> %m, i64 %vl) {
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; CHECK-LABEL: vfredusum:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
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; CHECK-NEXT: fsrmi a0, 0
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; CHECK-NEXT: vmv1r.v v11, v8
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; CHECK-NEXT: vfredusum.vs v11, v9, v10
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; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, ma
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; CHECK-NEXT: vmerge.vvm v8, v8, v11, v0
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; CHECK-NEXT: fsrm a0
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; CHECK-NEXT: ret
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%a = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv2f32(
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<vscale x 2 x float> %passthru,
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<vscale x 2 x float> %x,
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<vscale x 2 x float> %y,
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i64 0, i64 %vl)
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%b = call <vscale x 2 x float> @llvm.riscv.vmerge.nxv2f32.nxv2f32(<vscale x 2 x float> %passthru, <vscale x 2 x float> %passthru, <vscale x 2 x float> %a, <vscale x 2 x i1> %m, i64 %vl)
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ret <vscale x 2 x float> %b
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}
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; However we can fold it in if the mask is all ones.
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define <vscale x 2 x i32> @vredsum_allones_mask(<vscale x 2 x i32> %passthru, <vscale x 2 x i32> %x, <vscale x 2 x i32> %y, i64 %vl) {
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; CHECK-LABEL: vredsum_allones_mask:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
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; CHECK-NEXT: vmv1r.v v11, v8
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; CHECK-NEXT: vredsum.vs v11, v9, v10
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; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, ma
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; CHECK-NEXT: vmv.v.v v8, v11
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; CHECK-NEXT: ret
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%splat = insertelement <vscale x 2 x i1> poison, i1 -1, i32 0
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%mask = shufflevector <vscale x 2 x i1> %splat, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
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%a = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv2i32(
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<vscale x 2 x i32> %passthru,
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<vscale x 2 x i32> %x,
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<vscale x 2 x i32> %y,
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i64 %vl)
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%b = call <vscale x 2 x i32> @llvm.riscv.vmerge.nxv2i32.nxv2i32(<vscale x 2 x i32> %passthru, <vscale x 2 x i32> %passthru, <vscale x 2 x i32> %a, <vscale x 2 x i1> %mask, i64 %vl)
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ret <vscale x 2 x i32> %b
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}
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define <vscale x 2 x float> @vfredusum_allones_mask(<vscale x 2 x float> %passthru, <vscale x 2 x float> %x, <vscale x 2 x float> %y, i64 %vl) {
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; CHECK-LABEL: vfredusum_allones_mask:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
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; CHECK-NEXT: fsrmi a0, 0
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; CHECK-NEXT: vmv1r.v v11, v8
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; CHECK-NEXT: vfredusum.vs v11, v9, v10
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; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, ma
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; CHECK-NEXT: vmv.v.v v8, v11
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; CHECK-NEXT: fsrm a0
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; CHECK-NEXT: ret
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%splat = insertelement <vscale x 2 x i1> poison, i1 -1, i32 0
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%mask = shufflevector <vscale x 2 x i1> %splat, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
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%a = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv2f32(
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<vscale x 2 x float> %passthru,
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<vscale x 2 x float> %x,
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<vscale x 2 x float> %y,
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i64 0, i64 %vl)
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%b = call <vscale x 2 x float> @llvm.riscv.vmerge.nxv2f32.nxv2f32(<vscale x 2 x float> %passthru, <vscale x 2 x float> %passthru, <vscale x 2 x float> %a, <vscale x 2 x i1> %mask, i64 %vl)
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ret <vscale x 2 x float> %b
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}
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declare <vscale x 32 x i16> @llvm.riscv.vle.nxv32i16.i64(<vscale x 32 x i16>, <vscale x 32 x i16>* nocapture, i64)
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declare <vscale x 32 x i8> @llvm.riscv.vssubu.mask.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, <vscale x 32 x i1>, i64, i64 immarg)
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declare <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64)

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