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[RISCV][MachineCombiner] Pre-commit test for RVV reassociations
This is the pre-commit test for PR #88307.
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‎llvm/test/CodeGen/RISCV/rvv/vector-reassociations.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -mtriple=riscv32 -mattr='+v' -O3 %s -o - | FileCheck %s
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declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(
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<vscale x 1 x i8>,
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<vscale x 1 x i8>,
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<vscale x 1 x i8>,
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i32)
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declare <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(
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<vscale x 1 x i8>,
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<vscale x 1 x i8>,
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<vscale x 1 x i8>,
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<vscale x 1 x i1>,
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i32, i32)
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declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8(
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<vscale x 1 x i8>,
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<vscale x 1 x i8>,
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<vscale x 1 x i8>,
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i32)
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declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8(
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<vscale x 1 x i8>,
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<vscale x 1 x i8>,
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<vscale x 1 x i8>,
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i32)
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define <vscale x 1 x i8> @simple_vadd_vv(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
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; CHECK-LABEL: simple_vadd_vv:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
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; CHECK-NEXT: vadd.vv v9, v8, v9
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; CHECK-NEXT: vadd.vv v9, v8, v9
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; CHECK-NEXT: vadd.vv v8, v8, v9
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(
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<vscale x 1 x i8> undef,
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<vscale x 1 x i8> %0,
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<vscale x 1 x i8> %1,
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i32 %2)
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%b = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(
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<vscale x 1 x i8> undef,
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<vscale x 1 x i8> %0,
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<vscale x 1 x i8> %a,
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i32 %2)
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%c = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(
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<vscale x 1 x i8> undef,
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<vscale x 1 x i8> %0,
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<vscale x 1 x i8> %b,
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i32 %2)
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ret <vscale x 1 x i8> %c
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}
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define <vscale x 1 x i8> @simple_vadd_vsub_vv(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
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; CHECK-LABEL: simple_vadd_vsub_vv:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
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; CHECK-NEXT: vsub.vv v9, v8, v9
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; CHECK-NEXT: vadd.vv v9, v8, v9
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; CHECK-NEXT: vadd.vv v8, v8, v9
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8(
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<vscale x 1 x i8> undef,
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<vscale x 1 x i8> %0,
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<vscale x 1 x i8> %1,
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i32 %2)
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%b = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(
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<vscale x 1 x i8> undef,
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<vscale x 1 x i8> %0,
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<vscale x 1 x i8> %a,
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i32 %2)
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%c = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(
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<vscale x 1 x i8> undef,
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<vscale x 1 x i8> %0,
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<vscale x 1 x i8> %b,
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i32 %2)
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ret <vscale x 1 x i8> %c
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}
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define <vscale x 1 x i8> @simple_vmul_vv(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
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; CHECK-LABEL: simple_vmul_vv:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
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; CHECK-NEXT: vmul.vv v9, v8, v9
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; CHECK-NEXT: vmul.vv v9, v8, v9
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; CHECK-NEXT: vmul.vv v8, v8, v9
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8(
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<vscale x 1 x i8> undef,
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<vscale x 1 x i8> %0,
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<vscale x 1 x i8> %1,
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i32 %2)
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%b = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8(
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<vscale x 1 x i8> undef,
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<vscale x 1 x i8> %0,
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<vscale x 1 x i8> %a,
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i32 %2)
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%c = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8(
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<vscale x 1 x i8> undef,
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<vscale x 1 x i8> %0,
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<vscale x 1 x i8> %b,
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i32 %2)
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ret <vscale x 1 x i8> %c
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}
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; With passthru and masks.
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define <vscale x 1 x i8> @vadd_vv_passthru(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
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; CHECK-LABEL: vadd_vv_passthru:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma
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; CHECK-NEXT: vmv1r.v v10, v8
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; CHECK-NEXT: vadd.vv v10, v8, v9
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; CHECK-NEXT: vmv1r.v v9, v8
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; CHECK-NEXT: vadd.vv v9, v8, v10
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; CHECK-NEXT: vadd.vv v8, v8, v9
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(
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<vscale x 1 x i8> %0,
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<vscale x 1 x i8> %0,
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<vscale x 1 x i8> %1,
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i32 %2)
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%b = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(
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<vscale x 1 x i8> %0,
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<vscale x 1 x i8> %0,
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<vscale x 1 x i8> %a,
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i32 %2)
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%c = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(
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<vscale x 1 x i8> %0,
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<vscale x 1 x i8> %0,
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<vscale x 1 x i8> %b,
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i32 %2)
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ret <vscale x 1 x i8> %c
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}
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define <vscale x 1 x i8> @vadd_vv_passthru_negative(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
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; CHECK-LABEL: vadd_vv_passthru_negative:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma
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; CHECK-NEXT: vmv1r.v v10, v8
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; CHECK-NEXT: vadd.vv v10, v8, v9
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; CHECK-NEXT: vadd.vv v9, v8, v10
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; CHECK-NEXT: vadd.vv v8, v8, v9
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(
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<vscale x 1 x i8> %0,
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<vscale x 1 x i8> %0,
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<vscale x 1 x i8> %1,
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i32 %2)
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%b = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(
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<vscale x 1 x i8> %1,
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<vscale x 1 x i8> %0,
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<vscale x 1 x i8> %a,
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i32 %2)
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%c = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(
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<vscale x 1 x i8> %0,
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<vscale x 1 x i8> %0,
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<vscale x 1 x i8> %b,
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i32 %2)
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ret <vscale x 1 x i8> %c
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}
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define <vscale x 1 x i8> @vadd_vv_mask(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2, <vscale x 1 x i1> %m) nounwind {
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; CHECK-LABEL: vadd_vv_mask:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
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; CHECK-NEXT: vmv1r.v v10, v8
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; CHECK-NEXT: vadd.vv v10, v8, v9, v0.t
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; CHECK-NEXT: vmv1r.v v9, v8
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; CHECK-NEXT: vadd.vv v9, v8, v10, v0.t
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; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(
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<vscale x 1 x i8> %0,
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<vscale x 1 x i8> %0,
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<vscale x 1 x i8> %1,
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<vscale x 1 x i1> %m,
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i32 %2, i32 1)
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%b = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(
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<vscale x 1 x i8> %0,
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<vscale x 1 x i8> %0,
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<vscale x 1 x i8> %a,
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<vscale x 1 x i1> %m,
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i32 %2, i32 1)
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%c = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(
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<vscale x 1 x i8> %0,
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<vscale x 1 x i8> %0,
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<vscale x 1 x i8> %b,
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<vscale x 1 x i1> %m,
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i32 %2, i32 1)
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ret <vscale x 1 x i8> %c
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}
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define <vscale x 1 x i8> @vadd_vv_mask_negative(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2, <vscale x 1 x i1> %m) nounwind {
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; CHECK-LABEL: vadd_vv_mask_negative:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
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; CHECK-NEXT: vmv1r.v v10, v8
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; CHECK-NEXT: vadd.vv v10, v8, v9, v0.t
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; CHECK-NEXT: vmv1r.v v9, v8
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; CHECK-NEXT: vadd.vv v9, v8, v10, v0.t
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; CHECK-NEXT: vadd.vv v8, v8, v9
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(
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<vscale x 1 x i8> %0,
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<vscale x 1 x i8> %0,
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<vscale x 1 x i8> %1,
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<vscale x 1 x i1> %m,
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i32 %2, i32 1)
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%b = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(
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<vscale x 1 x i8> %0,
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<vscale x 1 x i8> %0,
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<vscale x 1 x i8> %a,
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<vscale x 1 x i1> %m,
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i32 %2, i32 1)
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%splat = insertelement <vscale x 1 x i1> poison, i1 1, i32 0
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%m2 = shufflevector <vscale x 1 x i1> %splat, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer
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%c = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(
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<vscale x 1 x i8> %0,
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<vscale x 1 x i8> %0,
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<vscale x 1 x i8> %b,
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<vscale x 1 x i1> %m2,
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i32 %2, i32 1)
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ret <vscale x 1 x i8> %c
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}
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