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nikolaypanchenkonikolaypanchenko
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removed rd argument from vcix.v.iv operation + rebase
1 parent e235452 commit fd5b264

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3 files changed

+40
-41
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3 files changed

+40
-41
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‎mlir/include/mlir/Dialect/LLVMIR/VCIXOps.td

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -62,7 +62,6 @@ def VCIX_BinaryImmOp
6262
Arguments<(ins VCIX_OpcodeAttr: $opcode,
6363
LLVM_AnyVector: $vs2,
6464
VCIX_ImmAttr: $imm,
65-
VCIX_Register: $rd,
6665
Optional<VCIX_VL>: $vl)> {
6766
string llvmBuilder = [{
6867
llvm::Type *xlen =getXlenType($opcode, moduleTranslation);

‎mlir/test/Target/LLVMIR/vcix-rv32.mlir

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -27,12 +27,12 @@ llvm.func @binary_vv(%arg0: vector<[4]xf32>, %arg1: vector<[4]xf32>, %vl: i32) -
2727
llvm.return %0 : vector<[4]xf32>
2828
}
2929

30-
// CHECK-LABEL: define <vscale x 4 x float> @binary_iv(<vscale x 4 x float> %0, i32 %1, i32 %2) {
31-
// CHECK-NEXT: %4 = call <vscale x 4 x float> @llvm.riscv.sf.vc.v.iv.se.nxv4f32.i32.nxv4f32.i32.i32(i32 3, <vscale x 4 x float> %0, i32 5, i32 %2)
32-
// CHECK-NEXT: ret <vscale x 4 x float> %4
30+
// CHECK-LABEL: define <vscale x 4 x float> @binary_iv(<vscale x 4 x float> %0, i32 %1) {
31+
// CHECK-NEXT: %3 = call <vscale x 4 x float> @llvm.riscv.sf.vc.v.iv.se.nxv4f32.i32.nxv4f32.i32.i32(i32 3, <vscale x 4 x float> %0, i32 5, i32 %1)
32+
// CHECK-NEXT: ret <vscale x 4 x float> %3
3333
// CHECK-NEXT: }
34-
llvm.func @binary_iv(%arg0: vector<[4]xf32>, %rd: i32, %vl: i32) -> vector<[4]xf32> {
35-
%0 = "vcix.v.iv"(%arg0, %rd, %vl) <{opcode = 3 : i32, imm = 5 : i32}> : (vector<[4]xf32>, i32, i32) -> vector<[4]xf32>
34+
llvm.func @binary_iv(%arg0: vector<[4]xf32>, %vl: i32) -> vector<[4]xf32> {
35+
%0 = "vcix.v.iv"(%arg0, %vl) <{opcode = 3 : i32, imm = 5 : i32}> : (vector<[4]xf32>, i32) -> vector<[4]xf32>
3636
llvm.return %0 : vector<[4]xf32>
3737
}
3838

@@ -63,12 +63,12 @@ llvm.func @binary_fixed_vv(%arg0: vector<4xf32>, %arg1: vector<4xf32>) -> vector
6363
llvm.return %0 : vector<4xf32>
6464
}
6565

66-
// CHECK-LABEL: define <4 x float> @binary_fixed_iv(<4 x float> %0, i32 %1) {
67-
// CHECK-NEXT: %3 = call <4 x float> @llvm.riscv.sf.vc.v.iv.se.v4f32.i32.v4f32.i32.i32(i32 3, <4 x float> %0, i32 5, i32 4)
68-
// CHECK-NEXT: ret <4 x float> %3
66+
// CHECK-LABEL: define <4 x float> @binary_fixed_iv(<4 x float> %0) {
67+
// CHECK-NEXT: %2 = call <4 x float> @llvm.riscv.sf.vc.v.iv.se.v4f32.i32.v4f32.i32.i32(i32 3, <4 x float> %0, i32 5, i32 4)
68+
// CHECK-NEXT: ret <4 x float> %2
6969
// CHECK-NEXT: }
70-
llvm.func @binary_fixed_iv(%arg0: vector<4xf32>, %rd: i32) -> vector<4xf32> {
71-
%0 = "vcix.v.iv"(%arg0, %rd) <{opcode = 3 : i32, imm = 5 : i32}> : (vector<4xf32>, i32) -> vector<4xf32>
70+
llvm.func @binary_fixed_iv(%arg0: vector<4xf32>) -> vector<4xf32> {
71+
%0 = "vcix.v.iv"(%arg0) <{opcode = 3 : i32, imm = 5 : i32}> : (vector<4xf32>) -> vector<4xf32>
7272
llvm.return %0 : vector<4xf32>
7373
}
7474

@@ -101,12 +101,12 @@ llvm.func @binary_i_vv(%arg0: vector<[4]xi32>, %arg1: vector<[4]xi32>, %vl: i32)
101101
llvm.return %0 : vector<[4]xi32>
102102
}
103103

104-
// CHECK-LABEL: define <vscale x 4 x i32> @binary_i_iv(<vscale x 4 x i32> %0, i32 %1, i32 %2) {
105-
// CHECK-NEXT: %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.iv.se.nxv4i32.i32.nxv4i32.i32.i32(i32 3, <vscale x 4 x i32> %0, i32 5, i32 %2)
106-
// CHECK-NEXT: ret <vscale x 4 x i32> %4
104+
// CHECK-LABEL: define <vscale x 4 x i32> @binary_i_iv(<vscale x 4 x i32> %0, i32 %1) {
105+
// CHECK-NEXT: %3 = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.iv.se.nxv4i32.i32.nxv4i32.i32.i32(i32 3, <vscale x 4 x i32> %0, i32 5, i32 %1)
106+
// CHECK-NEXT: ret <vscale x 4 x i32> %3
107107
// CHECK-NEXT: }
108-
llvm.func @binary_i_iv(%arg0: vector<[4]xi32>, %rd: i32, %vl: i32) -> vector<[4]xi32> {
109-
%0 = "vcix.v.iv"(%arg0, %rd, %vl) <{opcode = 3 : i32, imm = 5 : i32}> : (vector<[4]xi32>, i32, i32) -> vector<[4]xi32>
108+
llvm.func @binary_i_iv(%arg0: vector<[4]xi32>, %vl: i32) -> vector<[4]xi32> {
109+
%0 = "vcix.v.iv"(%arg0, %vl) <{opcode = 3 : i32, imm = 5 : i32}> : (vector<[4]xi32>, i32) -> vector<[4]xi32>
110110
llvm.return %0 : vector<[4]xi32>
111111
}
112112

@@ -137,11 +137,11 @@ llvm.func @binary_i_fixed_vv(%arg0: vector<4xi32>, %arg1: vector<4xi32>) -> vect
137137
llvm.return %0 : vector<4xi32>
138138
}
139139

140-
// CHECK-LABEL: define <4 x i32> @binary_i_fixed_iv(<4 x i32> %0, i32 %1) {
141-
// CHECK-NEXT: %3 = call <4 x i32> @llvm.riscv.sf.vc.v.iv.se.v4i32.i32.v4i32.i32.i32(i32 3, <4 x i32> %0, i32 5, i32 4)
142-
// CHECK-NEXT: ret <4 x i32> %3
140+
// CHECK-LABEL: define <4 x i32> @binary_i_fixed_iv(<4 x i32> %0) {
141+
// CHECK-NEXT: %2 = call <4 x i32> @llvm.riscv.sf.vc.v.iv.se.v4i32.i32.v4i32.i32.i32(i32 3, <4 x i32> %0, i32 5, i32 4)
142+
// CHECK-NEXT: ret <4 x i32> %2
143143
// CHECK-NEXT: }
144-
llvm.func @binary_i_fixed_iv(%arg0: vector<4xi32>, %rd: i32) -> vector<4xi32> {
145-
%0 = "vcix.v.iv"(%arg0, %rd) <{opcode = 3 : i32, imm = 5 : i32}> : (vector<4xi32>, i32) -> vector<4xi32>
144+
llvm.func @binary_i_fixed_iv(%arg0: vector<4xi32>) -> vector<4xi32> {
145+
%0 = "vcix.v.iv"(%arg0) <{opcode = 3 : i32, imm = 5 : i32}> : (vector<4xi32>) -> vector<4xi32>
146146
llvm.return %0 : vector<4xi32>
147147
}

‎mlir/test/Target/LLVMIR/vcix-rv64.mlir

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -28,12 +28,12 @@ llvm.func @binary_vv(%arg0: vector<[4]xf32>, %arg1: vector<[4]xf32>, %vl: i64) -
2828
llvm.return %0 : vector<[4]xf32>
2929
}
3030

31-
// CHECK-LABEL: define <vscale x 4 x float> @binary_iv(<vscale x 4 x float> %0, i64 %1, i64 %2) {
32-
// CHECK-NEXT: %4 = call <vscale x 4 x float> @llvm.riscv.sf.vc.v.iv.se.nxv4f32.i64.nxv4f32.i64.i64(i64 3, <vscale x 4 x float> %0, i64 5, i64 %2)
33-
// CHECK-NEXT: ret <vscale x 4 x float> %4
31+
// CHECK-LABEL: define <vscale x 4 x float> @binary_iv(<vscale x 4 x float> %0, i64 %1) {
32+
// CHECK-NEXT: %3 = call <vscale x 4 x float> @llvm.riscv.sf.vc.v.iv.se.nxv4f32.i64.nxv4f32.i64.i64(i64 3, <vscale x 4 x float> %0, i64 5, i64 %1)
33+
// CHECK-NEXT: ret <vscale x 4 x float> %3
3434
// CHECK-NEXT: }
35-
llvm.func @binary_iv(%arg0: vector<[4]xf32>, %rd: i64, %vl: i64) -> vector<[4]xf32> {
36-
%0 = "vcix.v.iv"(%arg0, %rd, %vl) <{opcode = 3 : i64, imm = 5 : i64}> : (vector<[4]xf32>, i64, i64) -> vector<[4]xf32>
35+
llvm.func @binary_iv(%arg0: vector<[4]xf32>, %vl: i64) -> vector<[4]xf32> {
36+
%0 = "vcix.v.iv"(%arg0, %vl) <{opcode = 3 : i64, imm = 5 : i64}> : (vector<[4]xf32>, i64) -> vector<[4]xf32>
3737
llvm.return %0 : vector<[4]xf32>
3838
}
3939

@@ -64,12 +64,12 @@ llvm.func @binary_fixed_vv(%arg0: vector<4xf32>, %arg1: vector<4xf32>) -> vector
6464
llvm.return %0 : vector<4xf32>
6565
}
6666

67-
// CHECK-LABEL: define <4 x float> @binary_fixed_iv(<4 x float> %0, i64 %1) {
68-
// CHECK-NEXT: %3 = call <4 x float> @llvm.riscv.sf.vc.v.iv.se.v4f32.i64.v4f32.i64.i64(i64 3, <4 x float> %0, i64 5, i64 4)
69-
// CHECK-NEXT: ret <4 x float> %3
67+
// CHECK-LABEL: define <4 x float> @binary_fixed_iv(<4 x float> %0) {
68+
// CHECK-NEXT: %2 = call <4 x float> @llvm.riscv.sf.vc.v.iv.se.v4f32.i64.v4f32.i64.i64(i64 3, <4 x float> %0, i64 5, i64 4)
69+
// CHECK-NEXT: ret <4 x float> %2
7070
// CHECK-NEXT: }
71-
llvm.func @binary_fixed_iv(%arg0: vector<4xf32>, %rd: i64) -> vector<4xf32> {
72-
%0 = "vcix.v.iv"(%arg0, %rd) <{opcode = 3 : i64, imm = 5 : i64}> : (vector<4xf32>, i64) -> vector<4xf32>
71+
llvm.func @binary_fixed_iv(%arg0: vector<4xf32>) -> vector<4xf32> {
72+
%0 = "vcix.v.iv"(%arg0) <{opcode = 3 : i64, imm = 5 : i64}> : (vector<4xf32>) -> vector<4xf32>
7373
llvm.return %0 : vector<4xf32>
7474
}
7575

@@ -102,12 +102,12 @@ llvm.func @binary_i_vv(%arg0: vector<[4]xi32>, %arg1: vector<[4]xi32>, %vl: i64)
102102
llvm.return %0 : vector<[4]xi32>
103103
}
104104

105-
// CHECK-LABEL: define <vscale x 4 x i32> @binary_i_iv(<vscale x 4 x i32> %0, i64 %1, i64 %2) {
106-
// CHECK-NEXT: %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.iv.se.nxv4i32.i64.nxv4i32.i64.i64(i64 3, <vscale x 4 x i32> %0, i64 5, i64 %2)
107-
// CHECK-NEXT: ret <vscale x 4 x i32> %4
105+
// CHECK-LABEL: define <vscale x 4 x i32> @binary_i_iv(<vscale x 4 x i32> %0, i64 %1) {
106+
// CHECK-NEXT: %3 = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.iv.se.nxv4i32.i64.nxv4i32.i64.i64(i64 3, <vscale x 4 x i32> %0, i64 5, i64 %1)
107+
// CHECK-NEXT: ret <vscale x 4 x i32> %3
108108
// CHECK-NEXT: }
109-
llvm.func @binary_i_iv(%arg0: vector<[4]xi32>, %rd: i64, %vl: i64) -> vector<[4]xi32> {
110-
%0 = "vcix.v.iv"(%arg0, %rd, %vl) <{opcode = 3 : i64, imm = 5 : i64}> : (vector<[4]xi32>, i64, i64) -> vector<[4]xi32>
109+
llvm.func @binary_i_iv(%arg0: vector<[4]xi32>, %vl: i64) -> vector<[4]xi32> {
110+
%0 = "vcix.v.iv"(%arg0, %vl) <{opcode = 3 : i64, imm = 5 : i64}> : (vector<[4]xi32>, i64) -> vector<[4]xi32>
111111
llvm.return %0 : vector<[4]xi32>
112112
}
113113

@@ -138,11 +138,11 @@ llvm.func @binary_i_fixed_vv(%arg0: vector<4xi32>, %arg1: vector<4xi32>) -> vect
138138
llvm.return %0 : vector<4xi32>
139139
}
140140

141-
// CHECK-LABEL: define <4 x i32> @binary_i_fixed_iv(<4 x i32> %0, i64 %1) {
142-
// CHECK-NEXT: %3 = call <4 x i32> @llvm.riscv.sf.vc.v.iv.se.v4i32.i64.v4i32.i64.i64(i64 3, <4 x i32> %0, i64 5, i64 4)
143-
// CHECK-NEXT: ret <4 x i32> %3
141+
// CHECK-LABEL: define <4 x i32> @binary_i_fixed_iv(<4 x i32> %0) {
142+
// CHECK-NEXT: %2 = call <4 x i32> @llvm.riscv.sf.vc.v.iv.se.v4i32.i64.v4i32.i64.i64(i64 3, <4 x i32> %0, i64 5, i64 4)
143+
// CHECK-NEXT: ret <4 x i32> %2
144144
// CHECK-NEXT: }
145-
llvm.func @binary_i_fixed_iv(%arg0: vector<4xi32>, %rd: i64) -> vector<4xi32> {
146-
%0 = "vcix.v.iv"(%arg0, %rd) <{opcode = 3 : i64, imm = 5 : i64}> : (vector<4xi32>, i64) -> vector<4xi32>
145+
llvm.func @binary_i_fixed_iv(%arg0: vector<4xi32>) -> vector<4xi32> {
146+
%0 = "vcix.v.iv"(%arg0) <{opcode = 3 : i64, imm = 5 : i64}> : (vector<4xi32>) -> vector<4xi32>
147147
llvm.return %0 : vector<4xi32>
148148
}

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