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[RISCV][GISel] Promote s32 G_SEXTLOAD/ZEXTLOAD on RV64.
1 parent 4a0c307 commit fd8d433

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5 files changed

+30
-140
lines changed

5 files changed

+30
-140
lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -284,8 +284,8 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
284284
{s32, p0, s32, getScalarMemAlign(32)},
285285
{p0, p0, sXLen, getScalarMemAlign(XLen)}});
286286
ExtLoadActions.legalForTypesWithMemDesc(
287-
{{s32, p0, s8, getScalarMemAlign(8)},
288-
{s32, p0, s16, getScalarMemAlign(16)}});
287+
{{sXLen, p0, s8, getScalarMemAlign(8)},
288+
{sXLen, p0, s16, getScalarMemAlign(16)}});
289289
if (XLen == 64) {
290290
LoadActions.legalForTypesWithMemDesc(
291291
{{s64, p0, s8, getScalarMemAlign(8)},
@@ -298,9 +298,7 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
298298
{s64, p0, s32, getScalarMemAlign(32)},
299299
{s64, p0, s64, getScalarMemAlign(64)}});
300300
ExtLoadActions.legalForTypesWithMemDesc(
301-
{{s64, p0, s8, getScalarMemAlign(8)},
302-
{s64, p0, s16, getScalarMemAlign(16)},
303-
{s64, p0, s32, getScalarMemAlign(32)}});
301+
{{s64, p0, s32, getScalarMemAlign(32)}});
304302
} else if (ST.hasStdExtD()) {
305303
LoadActions.legalForTypesWithMemDesc(
306304
{{s64, p0, s64, getScalarMemAlign(64)}});
@@ -382,7 +380,7 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
382380
.lowerIfMemSizeNotByteSizePow2()
383381
.lower();
384382

385-
ExtLoadActions.widenScalarToNextPow2(0).clampScalar(0, s32, sXLen).lower();
383+
ExtLoadActions.widenScalarToNextPow2(0).clampScalar(0, sXLen, sXLen).lower();
386384

387385
getActionDefinitionsBuilder({G_PTR_ADD, G_PTRMASK}).legalFor({{p0, sXLen}});
388386

‎llvm/lib/Target/RISCV/RISCVGISel.td

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -187,12 +187,8 @@ def zext_is_sext : PatFrag<(ops node:$src), (zext node:$src), [{
187187
}]>;
188188

189189
let Predicates = [IsRV64] in {
190-
def : LdPat<sextloadi8, LB, i32>;
191190
def : LdPat<extloadi8, LBU, i32>; // Prefer unsigned due to no c.lb in Zcb.
192-
def : LdPat<sextloadi16, LH, i32>;
193191
def : LdPat<extloadi16, LH, i32>;
194-
def : LdPat<zextloadi8, LBU, i32>;
195-
def : LdPat<zextloadi16, LHU, i32>;
196192

197193
def : StPat<truncstorei8, SB, GPR, i32>;
198194
def : StPat<truncstorei16, SH, GPR, i32>;

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir

Lines changed: 0 additions & 92 deletions
Original file line numberDiff line numberDiff line change
@@ -17,10 +17,6 @@
1717
define void @load_i8_i32(ptr %addr) { ret void }
1818
define void @load_i16_i32(ptr %addr) { ret void }
1919
define void @load_i32_i32(ptr %addr) { ret void }
20-
define void @zextload_i8_i32(ptr %addr) { ret void }
21-
define void @zextload_i16_i32(ptr %addr) { ret void }
22-
define void @sextload_i8_i32(ptr %addr) { ret void }
23-
define void @sextload_i16_i32(ptr %addr) { ret void }
2420
define void @load_fi_i64() {
2521
%ptr0 = alloca i64
2622
ret void
@@ -338,94 +334,6 @@ body: |
338334
$x10 = COPY %5(s64)
339335
PseudoRET implicit $x10
340336
341-
...
342-
---
343-
name: zextload_i8_i32
344-
legalized: true
345-
regBankSelected: true
346-
tracksRegLiveness: true
347-
body: |
348-
bb.0:
349-
liveins: $x10
350-
; CHECK-LABEL: name: zextload_i8_i32
351-
; CHECK: liveins: $x10
352-
; CHECK-NEXT: {{ $}}
353-
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
354-
; CHECK-NEXT: [[LBU:%[0-9]+]]:gpr = LBU [[COPY]], 0 :: (load (s8))
355-
; CHECK-NEXT: $x10 = COPY [[LBU]]
356-
; CHECK-NEXT: PseudoRET implicit $x10
357-
%0:gprb(p0) = COPY $x10
358-
%9:gprb(s32) = G_ZEXTLOAD %0(p0) :: (load (s8))
359-
%5:gprb(s64) = G_ANYEXT %9(s32)
360-
$x10 = COPY %5(s64)
361-
PseudoRET implicit $x10
362-
363-
...
364-
---
365-
name: zextload_i16_i32
366-
legalized: true
367-
regBankSelected: true
368-
tracksRegLiveness: true
369-
body: |
370-
bb.0:
371-
liveins: $x10, $x11
372-
; CHECK-LABEL: name: zextload_i16_i32
373-
; CHECK: liveins: $x10, $x11
374-
; CHECK-NEXT: {{ $}}
375-
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
376-
; CHECK-NEXT: [[LHU:%[0-9]+]]:gpr = LHU [[COPY]], 0 :: (load (s16))
377-
; CHECK-NEXT: $x10 = COPY [[LHU]]
378-
; CHECK-NEXT: PseudoRET implicit $x10
379-
%0:gprb(p0) = COPY $x10
380-
%9:gprb(s32) = G_ZEXTLOAD %0(p0) :: (load (s16))
381-
%5:gprb(s64) = G_ANYEXT %9(s32)
382-
$x10 = COPY %5(s64)
383-
PseudoRET implicit $x10
384-
385-
...
386-
---
387-
name: sextload_i8_i32
388-
legalized: true
389-
regBankSelected: true
390-
tracksRegLiveness: true
391-
body: |
392-
bb.0:
393-
liveins: $x10
394-
; CHECK-LABEL: name: sextload_i8_i32
395-
; CHECK: liveins: $x10
396-
; CHECK-NEXT: {{ $}}
397-
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
398-
; CHECK-NEXT: [[LB:%[0-9]+]]:gpr = LB [[COPY]], 0 :: (load (s8))
399-
; CHECK-NEXT: $x10 = COPY [[LB]]
400-
; CHECK-NEXT: PseudoRET implicit $x10
401-
%0:gprb(p0) = COPY $x10
402-
%9:gprb(s32) = G_SEXTLOAD %0(p0) :: (load (s8))
403-
%5:gprb(s64) = G_ANYEXT %9(s32)
404-
$x10 = COPY %5(s64)
405-
PseudoRET implicit $x10
406-
407-
...
408-
---
409-
name: sextload_i16_i32
410-
legalized: true
411-
regBankSelected: true
412-
tracksRegLiveness: true
413-
body: |
414-
bb.0:
415-
liveins: $x10
416-
; CHECK-LABEL: name: sextload_i16_i32
417-
; CHECK: liveins: $x10
418-
; CHECK-NEXT: {{ $}}
419-
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
420-
; CHECK-NEXT: [[LH:%[0-9]+]]:gpr = LH [[COPY]], 0 :: (load (s16))
421-
; CHECK-NEXT: $x10 = COPY [[LH]]
422-
; CHECK-NEXT: PseudoRET implicit $x10
423-
%0:gprb(p0) = COPY $x10
424-
%9:gprb(s32) = G_SEXTLOAD %0(p0) :: (load (s16))
425-
%5:gprb(s64) = G_ANYEXT %9(s32)
426-
$x10 = COPY %5(s64)
427-
PseudoRET implicit $x10
428-
429337
...
430338
---
431339
name: load_fi_i64

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-extload-rv64.mir

Lines changed: 12 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -12,9 +12,8 @@ body: |
1212
; CHECK: liveins: $x10
1313
; CHECK-NEXT: {{ $}}
1414
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
15-
; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
16-
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ZEXTLOAD]](s32)
17-
; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
15+
; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
16+
; CHECK-NEXT: $x10 = COPY [[ZEXTLOAD]](s64)
1817
; CHECK-NEXT: PseudoRET implicit $x10
1918
%0:_(p0) = COPY $x10
2019
%2:_(s16) = G_ZEXTLOAD %0(p0) :: (load (s8))
@@ -33,9 +32,8 @@ body: |
3332
; CHECK: liveins: $x10
3433
; CHECK-NEXT: {{ $}}
3534
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
36-
; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
37-
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ZEXTLOAD]](s32)
38-
; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
35+
; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
36+
; CHECK-NEXT: $x10 = COPY [[ZEXTLOAD]](s64)
3937
; CHECK-NEXT: PseudoRET implicit $x10
4038
%0:_(p0) = COPY $x10
4139
%2:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s8))
@@ -54,9 +52,8 @@ body: |
5452
; CHECK: liveins: $x10
5553
; CHECK-NEXT: {{ $}}
5654
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
57-
; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16))
58-
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ZEXTLOAD]](s32)
59-
; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
55+
; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16))
56+
; CHECK-NEXT: $x10 = COPY [[ZEXTLOAD]](s64)
6057
; CHECK-NEXT: PseudoRET implicit $x10
6158
%0:_(p0) = COPY $x10
6259
%2:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s16))
@@ -152,9 +149,8 @@ body: |
152149
; CHECK: liveins: $x10
153150
; CHECK-NEXT: {{ $}}
154151
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
155-
; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
156-
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SEXTLOAD]](s32)
157-
; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
152+
; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
153+
; CHECK-NEXT: $x10 = COPY [[SEXTLOAD]](s64)
158154
; CHECK-NEXT: PseudoRET implicit $x10
159155
%0:_(p0) = COPY $x10
160156
%2:_(s16) = G_SEXTLOAD %0(p0) :: (load (s8))
@@ -173,9 +169,8 @@ body: |
173169
; CHECK: liveins: $x10
174170
; CHECK-NEXT: {{ $}}
175171
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
176-
; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
177-
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SEXTLOAD]](s32)
178-
; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
172+
; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
173+
; CHECK-NEXT: $x10 = COPY [[SEXTLOAD]](s64)
179174
; CHECK-NEXT: PseudoRET implicit $x10
180175
%0:_(p0) = COPY $x10
181176
%2:_(s32) = G_SEXTLOAD %0(p0) :: (load (s8))
@@ -194,9 +189,8 @@ body: |
194189
; CHECK: liveins: $x10
195190
; CHECK-NEXT: {{ $}}
196191
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
197-
; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16))
198-
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SEXTLOAD]](s32)
199-
; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
192+
; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load (s16))
193+
; CHECK-NEXT: $x10 = COPY [[SEXTLOAD]](s64)
200194
; CHECK-NEXT: PseudoRET implicit $x10
201195
%0:_(p0) = COPY $x10
202196
%2:_(s32) = G_SEXTLOAD %0(p0) :: (load (s16))

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv64.mir

Lines changed: 14 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -271,15 +271,14 @@ body: |
271271
; CHECK: liveins: $x10
272272
; CHECK-NEXT: {{ $}}
273273
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
274-
; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
274+
; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
275275
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
276276
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
277277
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s8) from unknown-address + 1)
278278
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
279279
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
280280
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C1]](s64)
281-
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[ZEXTLOAD]](s32)
282-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[ANYEXT1]]
281+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[ZEXTLOAD]]
283282
; CHECK-NEXT: $x10 = COPY [[OR]](s64)
284283
; CHECK-NEXT: PseudoRET implicit $x10
285284
;
@@ -319,27 +318,23 @@ body: |
319318
; CHECK: liveins: $x10
320319
; CHECK-NEXT: {{ $}}
321320
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
322-
; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
321+
; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
323322
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
324323
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
325-
; CHECK-NEXT: [[ZEXTLOAD1:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[PTR_ADD]](p0) :: (load (s8) from unknown-address + 1)
324+
; CHECK-NEXT: [[ZEXTLOAD1:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD]](p0) :: (load (s8) from unknown-address + 1)
326325
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
327-
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ZEXTLOAD1]](s32)
328-
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C1]](s64)
329-
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[ZEXTLOAD]](s32)
330-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[ANYEXT1]]
326+
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXTLOAD1]], [[C1]](s64)
327+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[ZEXTLOAD]]
331328
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
332329
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
333-
; CHECK-NEXT: [[ZEXTLOAD2:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[PTR_ADD1]](p0) :: (load (s8) from unknown-address + 2)
330+
; CHECK-NEXT: [[ZEXTLOAD2:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD1]](p0) :: (load (s8) from unknown-address + 2)
334331
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)
335332
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 3)
336-
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
337-
; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
338-
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT2]], [[C3]](s64)
339-
; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[ZEXTLOAD2]](s32)
340-
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[ANYEXT3]]
341-
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
342-
; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[OR1]], [[C4]](s64)
333+
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
334+
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C1]](s64)
335+
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[ZEXTLOAD2]]
336+
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
337+
; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[OR1]], [[C3]](s64)
343338
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL2]], [[OR]]
344339
; CHECK-NEXT: $x10 = COPY [[OR2]](s64)
345340
; CHECK-NEXT: PseudoRET implicit $x10
@@ -380,15 +375,14 @@ body: |
380375
; CHECK: liveins: $x10
381376
; CHECK-NEXT: {{ $}}
382377
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
383-
; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16))
378+
; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16))
384379
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
385380
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
386381
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s16) from unknown-address + 2)
387382
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
388383
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
389384
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C1]](s64)
390-
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[ZEXTLOAD]](s32)
391-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[ANYEXT1]]
385+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[ZEXTLOAD]]
392386
; CHECK-NEXT: $x10 = COPY [[OR]](s64)
393387
; CHECK-NEXT: PseudoRET implicit $x10
394388
;

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