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[X86] Handle BSF/BSF "zero-input fall through" behaviour
Intel docs have been updated to be similar to AMD and now describe BSF/BSF as not changing the destination register if the input value was zero, which allows us to support CTTZ/CTLZ zero-input cases by setting the destination to support a NumBits result (BSR is a bit messy as it has to XOR'd to create a CTLZ result). VIA/Zhaoxin x86_64 CPUs have also been confirmed to match this behaviour. There are still some limits to this - its only supported for x86_64 capable processors (and I've only enabled it for x86_64 codegen), and there are some Intel CPUs that don't correctly zero the upper 32-bits of a pass through register when used for BSR32/BSF32 with a zero source value (i.e. the whole 64bits may get p[assed through).
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+210
-214
lines changed

16 files changed

+210
-214
lines changed

‎llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 40 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -434,11 +434,11 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
434434

435435
if (!Subtarget.hasBMI()) {
436436
setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
437-
setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Legal);
437+
setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Custom);
438438
if (Subtarget.is64Bit()) {
439439
setOperationPromotedToType(ISD::CTTZ , MVT::i32, MVT::i64);
440440
setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
441-
setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Legal);
441+
setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Custom);
442442
}
443443
}
444444

@@ -3386,15 +3386,18 @@ bool X86TargetLowering::shouldFormOverflowOp(unsigned Opcode, EVT VT,
33863386
}
33873387

33883388
bool X86TargetLowering::isCheapToSpeculateCttz(Type *Ty) const {
3389-
// Speculate cttz only if we can directly use TZCNT or can promote to i32/i64.
3389+
// Speculate cttz only if we can directly use TZCNT/CMOV, can promote to
3390+
// i32/i64 or can rely on BSF passthrough value.
33903391
return Subtarget.hasBMI() || Subtarget.canUseCMOV() ||
3391-
(!Ty->isVectorTy() &&
3392-
Ty->getScalarSizeInBits() < (Subtarget.is64Bit() ? 64u : 32u));
3392+
Subtarget.hasBitScanPassThrough() ||
3393+
(!Ty->isVectorTy() && Ty->getScalarSizeInBits() < 32u);
33933394
}
33943395

33953396
bool X86TargetLowering::isCheapToSpeculateCtlz(Type *Ty) const {
3396-
// Speculate ctlz only if we can directly use LZCNT.
3397-
return Subtarget.hasLZCNT() || Subtarget.canUseCMOV();
3397+
// Speculate ctlz only if we can directly use LZCNT/CMOV, or can rely on BSR
3398+
// passthrough value.
3399+
return Subtarget.hasLZCNT() || Subtarget.canUseCMOV() ||
3400+
Subtarget.hasBitScanPassThrough();
33983401
}
33993402

34003403
bool X86TargetLowering::ShouldShrinkFPConstant(EVT VT) const {
@@ -28694,11 +28697,18 @@ static SDValue LowerCTLZ(SDValue Op, const X86Subtarget &Subtarget,
2869428697
Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
2869528698
}
2869628699

28700+
// Check if we can safely pass a result though BSR for zero sources.
28701+
SDValue PassThru = DAG.getUNDEF(OpVT);
28702+
if (Opc == ISD::CTLZ && Subtarget.hasBitScanPassThrough() &&
28703+
!DAG.isKnownNeverZero(Op))
28704+
PassThru = DAG.getConstant(NumBits + NumBits - 1, dl, OpVT);
28705+
2869728706
// Issue a bsr (scan bits in reverse) which also sets EFLAGS.
2869828707
SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
28699-
Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
28708+
Op = DAG.getNode(X86ISD::BSR, dl, VTs, PassThru, Op);
2870028709

28701-
if (Opc == ISD::CTLZ) {
28710+
// Skip CMOV if we're using a pass through value.
28711+
if (Opc == ISD::CTLZ && PassThru.isUndef()) {
2870228712
// If src is zero (i.e. bsr sets ZF), returns NumBits.
2870328713
SDValue Ops[] = {Op, DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
2870428714
DAG.getTargetConstant(X86::COND_E, dl, MVT::i8),
@@ -28721,16 +28731,22 @@ static SDValue LowerCTTZ(SDValue Op, const X86Subtarget &Subtarget,
2872128731
unsigned NumBits = VT.getScalarSizeInBits();
2872228732
SDValue N0 = Op.getOperand(0);
2872328733
SDLoc dl(Op);
28734+
unsigned Opc = Op.getOpcode();
28735+
bool NonZeroSrc = DAG.isKnownNeverZero(N0);
28736+
28737+
assert(!VT.isVector() && "Only scalar CTTZ requires custom lowering");
2872428738

28725-
assert(!VT.isVector() && Op.getOpcode() == ISD::CTTZ &&
28726-
"Only scalar CTTZ requires custom lowering");
28739+
// Check if we can safely pass a result though BSF for zero sources.
28740+
SDValue PassThru = DAG.getUNDEF(VT);
28741+
if (Opc == ISD::CTTZ && !NonZeroSrc && Subtarget.hasBitScanPassThrough())
28742+
PassThru = DAG.getConstant(NumBits, dl, VT);
2872728743

2872828744
// Issue a bsf (scan bits forward) which also sets EFLAGS.
2872928745
SDVTList VTs = DAG.getVTList(VT, MVT::i32);
28730-
Op = DAG.getNode(X86ISD::BSF, dl, VTs, N0);
28746+
Op = DAG.getNode(X86ISD::BSF, dl, VTs, PassThru, N0);
2873128747

28732-
// If src is known never zero we can skip the CMOV.
28733-
if (DAG.isKnownNeverZero(N0))
28748+
// Skip CMOV if src is never zero or we're using a pass through value.
28749+
if (Opc != ISD::CTTZ || NonZeroSrc || !PassThru.isUndef())
2873428750
return Op;
2873528751

2873628752
// If src is zero (i.e. bsf sets ZF), returns NumBits.
@@ -38194,12 +38210,18 @@ void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
3819438210
Known = KnownBits::mul(Known, Known2);
3819538211
break;
3819638212
}
38197-
case X86ISD::BSR:
38198-
// BSR(0) is undef, but any use of BSR already accounts for non-zero inputs.
38199-
// Similar KnownBits behaviour to CTLZ_ZERO_UNDEF.
38213+
case X86ISD::BSR: {
3820038214
// TODO: Bound with input known bits?
3820138215
Known.Zero.setBitsFrom(Log2_32(BitWidth));
38216+
38217+
if (!Op.getOperand(0).isUndef() &&
38218+
!DAG.isKnownNeverZero(Op.getOperand(1), Depth + 1)) {
38219+
KnownBits Known2;
38220+
Known2 = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
38221+
Known = Known.intersectWith(Known2);
38222+
}
3820238223
break;
38224+
}
3820338225
case X86ISD::SETCC:
3820438226
Known.Zero.setBitsFrom(1);
3820538227
break;
@@ -54244,7 +54266,7 @@ static SDValue combineXorSubCTLZ(SDNode *N, const SDLoc &DL, SelectionDAG &DAG,
5424454266
}
5424554267

5424654268
SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
54247-
Op = DAG.getNode(X86ISD::BSR, DL, VTs, Op);
54269+
Op = DAG.getNode(X86ISD::BSR, DL, VTs, DAG.getUNDEF(OpVT), Op);
5424854270
if (VT == MVT::i8)
5424954271
Op = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, Op);
5425054272

‎llvm/lib/Target/X86/X86InstrCompiler.td

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2212,14 +2212,6 @@ def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
22122212
def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2),
22132213
(IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
22142214

2215-
// Bit scan instruction patterns to match explicit zero-undef behavior.
2216-
def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>;
2217-
def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>;
2218-
def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr GR64:$src)>;
2219-
def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm addr:$src)>;
2220-
def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm addr:$src)>;
2221-
def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm addr:$src)>;
2222-
22232215
// When HasMOVBE is enabled it is possible to get a non-legalized
22242216
// register-register 16 bit bswap. This maps it to a ROL instruction.
22252217
let Predicates = [HasMOVBE] in {

‎llvm/lib/Target/X86/X86InstrFragments.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -134,8 +134,8 @@ def SDTX86Cmpccxadd : SDTypeProfile<1, 4, [SDTCisSameAs<0, 2>,
134134
def X86MFence : SDNode<"X86ISD::MFENCE", SDTNone, [SDNPHasChain]>;
135135

136136

137-
def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
138-
def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
137+
def X86bsf : SDNode<"X86ISD::BSF", SDTBinaryArithWithFlags>;
138+
def X86bsr : SDNode<"X86ISD::BSR", SDTBinaryArithWithFlags>;
139139
def X86fshl : SDNode<"X86ISD::FSHL", SDTIntShiftDOp>;
140140
def X86fshr : SDNode<"X86ISD::FSHR", SDTIntShiftDOp>;
141141

‎llvm/lib/Target/X86/X86InstrMisc.td

Lines changed: 25 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -247,55 +247,55 @@ def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
247247
} // Constraints = "$src = $dst", SchedRW
248248

249249
// Bit scan instructions.
250-
let Defs = [EFLAGS] in {
251-
def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
250+
let Defs = [EFLAGS], Constraints = "$fallback = $dst" in {
251+
def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$fallback, GR16:$src),
252252
"bsf{w}\t{$src, $dst|$dst, $src}",
253-
[(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>,
253+
[(set GR16:$dst, EFLAGS, (X86bsf GR16:$fallback, GR16:$src))]>,
254254
TB, OpSize16, Sched<[WriteBSF]>;
255-
def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
255+
def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins GR16:$fallback, i16mem:$src),
256256
"bsf{w}\t{$src, $dst|$dst, $src}",
257-
[(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>,
257+
[(set GR16:$dst, EFLAGS, (X86bsf GR16:$fallback, (loadi16 addr:$src)))]>,
258258
TB, OpSize16, Sched<[WriteBSFLd]>;
259-
def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
259+
def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$fallback, GR32:$src),
260260
"bsf{l}\t{$src, $dst|$dst, $src}",
261-
[(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>,
261+
[(set GR32:$dst, EFLAGS, (X86bsf GR32:$fallback, GR32:$src))]>,
262262
TB, OpSize32, Sched<[WriteBSF]>;
263-
def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
263+
def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins GR32:$fallback, i32mem:$src),
264264
"bsf{l}\t{$src, $dst|$dst, $src}",
265-
[(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>,
265+
[(set GR32:$dst, EFLAGS, (X86bsf GR32:$fallback, (loadi32 addr:$src)))]>,
266266
TB, OpSize32, Sched<[WriteBSFLd]>;
267-
def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
267+
def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$fallback, GR64:$src),
268268
"bsf{q}\t{$src, $dst|$dst, $src}",
269-
[(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))]>,
269+
[(set GR64:$dst, EFLAGS, (X86bsf GR64:$fallback, GR64:$src))]>,
270270
TB, Sched<[WriteBSF]>;
271-
def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
271+
def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins GR64:$fallback, i64mem:$src),
272272
"bsf{q}\t{$src, $dst|$dst, $src}",
273-
[(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))]>,
273+
[(set GR64:$dst, EFLAGS, (X86bsf GR64:$fallback, (loadi64 addr:$src)))]>,
274274
TB, Sched<[WriteBSFLd]>;
275275

276-
def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
276+
def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$fallback, GR16:$src),
277277
"bsr{w}\t{$src, $dst|$dst, $src}",
278-
[(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>,
278+
[(set GR16:$dst, EFLAGS, (X86bsr GR16:$fallback, GR16:$src))]>,
279279
TB, OpSize16, Sched<[WriteBSR]>;
280-
def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
280+
def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins GR16:$fallback, i16mem:$src),
281281
"bsr{w}\t{$src, $dst|$dst, $src}",
282-
[(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>,
282+
[(set GR16:$dst, EFLAGS, (X86bsr GR16:$fallback, (loadi16 addr:$src)))]>,
283283
TB, OpSize16, Sched<[WriteBSRLd]>;
284-
def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
284+
def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$fallback, GR32:$src),
285285
"bsr{l}\t{$src, $dst|$dst, $src}",
286-
[(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>,
286+
[(set GR32:$dst, EFLAGS, (X86bsr GR32:$fallback, GR32:$src))]>,
287287
TB, OpSize32, Sched<[WriteBSR]>;
288-
def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
288+
def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins GR32:$fallback, i32mem:$src),
289289
"bsr{l}\t{$src, $dst|$dst, $src}",
290-
[(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>,
290+
[(set GR32:$dst, EFLAGS, (X86bsr GR32:$fallback, (loadi32 addr:$src)))]>,
291291
TB, OpSize32, Sched<[WriteBSRLd]>;
292-
def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
292+
def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$fallback, GR64:$src),
293293
"bsr{q}\t{$src, $dst|$dst, $src}",
294-
[(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))]>,
294+
[(set GR64:$dst, EFLAGS, (X86bsr GR64:$fallback, GR64:$src))]>,
295295
TB, Sched<[WriteBSR]>;
296-
def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
296+
def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins GR64:$fallback, i64mem:$src),
297297
"bsr{q}\t{$src, $dst|$dst, $src}",
298-
[(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))]>,
298+
[(set GR64:$dst, EFLAGS, (X86bsr GR64:$fallback, (loadi64 addr:$src)))]>,
299299
TB, Sched<[WriteBSRLd]>;
300300
} // Defs = [EFLAGS]
301301

‎llvm/lib/Target/X86/X86Subtarget.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -263,6 +263,11 @@ class X86Subtarget final : public X86GenSubtargetInfo {
263263
return hasBWI() && useAVX512Regs();
264264
}
265265

266+
// Returns true if the destination register of a BSF/BSR instruction is
267+
// not touched if the source register is zero.
268+
// NOTE: i32->i64 implicit zext isn't guaranteed by BSR/BSF pass through.
269+
bool hasBitScanPassThrough() const { return is64Bit(); }
270+
266271
bool isXRaySupported() const override { return is64Bit(); }
267272

268273
/// Use clflush if we have SSE2 or we're on x86-64 (even if we asked for

‎llvm/test/CodeGen/X86/bit_ceil.ll

Lines changed: 4 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -10,9 +10,8 @@ define i32 @bit_ceil_i32(i32 %x) {
1010
; NOBMI: # %bb.0:
1111
; NOBMI-NEXT: # kill: def $edi killed $edi def $rdi
1212
; NOBMI-NEXT: leal -1(%rdi), %eax
13-
; NOBMI-NEXT: bsrl %eax, %eax
1413
; NOBMI-NEXT: movl $63, %ecx
15-
; NOBMI-NEXT: cmovnel %eax, %ecx
14+
; NOBMI-NEXT: bsrl %eax, %ecx
1615
; NOBMI-NEXT: xorl $31, %ecx
1716
; NOBMI-NEXT: negb %cl
1817
; NOBMI-NEXT: movl $1, %edx
@@ -47,9 +46,8 @@ define i32 @bit_ceil_i32(i32 %x) {
4746
define i32 @bit_ceil_i32_plus1(i32 noundef %x) {
4847
; NOBMI-LABEL: bit_ceil_i32_plus1:
4948
; NOBMI: # %bb.0: # %entry
50-
; NOBMI-NEXT: bsrl %edi, %eax
5149
; NOBMI-NEXT: movl $63, %ecx
52-
; NOBMI-NEXT: cmovnel %eax, %ecx
50+
; NOBMI-NEXT: bsrl %edi, %ecx
5351
; NOBMI-NEXT: xorl $31, %ecx
5452
; NOBMI-NEXT: negb %cl
5553
; NOBMI-NEXT: movl $1, %edx
@@ -86,9 +84,8 @@ define i64 @bit_ceil_i64(i64 %x) {
8684
; NOBMI-LABEL: bit_ceil_i64:
8785
; NOBMI: # %bb.0:
8886
; NOBMI-NEXT: leaq -1(%rdi), %rax
89-
; NOBMI-NEXT: bsrq %rax, %rax
9087
; NOBMI-NEXT: movl $127, %ecx
91-
; NOBMI-NEXT: cmovneq %rax, %rcx
88+
; NOBMI-NEXT: bsrq %rax, %rcx
9289
; NOBMI-NEXT: xorl $63, %ecx
9390
; NOBMI-NEXT: negb %cl
9491
; NOBMI-NEXT: movl $1, %edx
@@ -122,9 +119,8 @@ define i64 @bit_ceil_i64(i64 %x) {
122119
define i64 @bit_ceil_i64_plus1(i64 noundef %x) {
123120
; NOBMI-LABEL: bit_ceil_i64_plus1:
124121
; NOBMI: # %bb.0: # %entry
125-
; NOBMI-NEXT: bsrq %rdi, %rax
126122
; NOBMI-NEXT: movl $127, %ecx
127-
; NOBMI-NEXT: cmovneq %rax, %rcx
123+
; NOBMI-NEXT: bsrq %rdi, %rcx
128124
; NOBMI-NEXT: xorl $63, %ecx
129125
; NOBMI-NEXT: negb %cl
130126
; NOBMI-NEXT: movl $1, %edx

‎llvm/test/CodeGen/X86/combine-or.ll

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -227,9 +227,8 @@ define i64 @PR89533(<64 x i8> %a0) {
227227
; SSE-NEXT: orl %eax, %edx
228228
; SSE-NEXT: shlq $32, %rdx
229229
; SSE-NEXT: orq %rcx, %rdx
230-
; SSE-NEXT: bsfq %rdx, %rcx
231230
; SSE-NEXT: movl $64, %eax
232-
; SSE-NEXT: cmovneq %rcx, %rax
231+
; SSE-NEXT: rep bsfq %rdx, %rax
233232
; SSE-NEXT: retq
234233
;
235234
; AVX1-LABEL: PR89533:
@@ -255,9 +254,8 @@ define i64 @PR89533(<64 x i8> %a0) {
255254
; AVX1-NEXT: orl %eax, %edx
256255
; AVX1-NEXT: shlq $32, %rdx
257256
; AVX1-NEXT: orq %rcx, %rdx
258-
; AVX1-NEXT: bsfq %rdx, %rcx
259257
; AVX1-NEXT: movl $64, %eax
260-
; AVX1-NEXT: cmovneq %rcx, %rax
258+
; AVX1-NEXT: rep bsfq %rdx, %rax
261259
; AVX1-NEXT: vzeroupper
262260
; AVX1-NEXT: retq
263261
;

‎llvm/test/CodeGen/X86/ctlo.ll

Lines changed: 5 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -44,10 +44,9 @@ define i8 @ctlo_i8(i8 %x) {
4444
; X64-LABEL: ctlo_i8:
4545
; X64: # %bb.0:
4646
; X64-NEXT: notb %dil
47-
; X64-NEXT: movzbl %dil, %eax
48-
; X64-NEXT: bsrl %eax, %ecx
47+
; X64-NEXT: movzbl %dil, %ecx
4948
; X64-NEXT: movl $15, %eax
50-
; X64-NEXT: cmovnel %ecx, %eax
49+
; X64-NEXT: bsrl %ecx, %eax
5150
; X64-NEXT: xorl $7, %eax
5251
; X64-NEXT: # kill: def $al killed $al killed $eax
5352
; X64-NEXT: retq
@@ -146,9 +145,8 @@ define i16 @ctlo_i16(i16 %x) {
146145
; X64-LABEL: ctlo_i16:
147146
; X64: # %bb.0:
148147
; X64-NEXT: notl %edi
149-
; X64-NEXT: bsrw %di, %cx
150148
; X64-NEXT: movw $31, %ax
151-
; X64-NEXT: cmovnew %cx, %ax
149+
; X64-NEXT: bsrw %di, %ax
152150
; X64-NEXT: xorl $15, %eax
153151
; X64-NEXT: # kill: def $ax killed $ax killed $eax
154152
; X64-NEXT: retq
@@ -232,9 +230,8 @@ define i32 @ctlo_i32(i32 %x) {
232230
; X64-LABEL: ctlo_i32:
233231
; X64: # %bb.0:
234232
; X64-NEXT: notl %edi
235-
; X64-NEXT: bsrl %edi, %ecx
236233
; X64-NEXT: movl $63, %eax
237-
; X64-NEXT: cmovnel %ecx, %eax
234+
; X64-NEXT: bsrl %edi, %eax
238235
; X64-NEXT: xorl $31, %eax
239236
; X64-NEXT: retq
240237
;
@@ -335,9 +332,8 @@ define i64 @ctlo_i64(i64 %x) {
335332
; X64-LABEL: ctlo_i64:
336333
; X64: # %bb.0:
337334
; X64-NEXT: notq %rdi
338-
; X64-NEXT: bsrq %rdi, %rcx
339335
; X64-NEXT: movl $127, %eax
340-
; X64-NEXT: cmovneq %rcx, %rax
336+
; X64-NEXT: bsrq %rdi, %rax
341337
; X64-NEXT: xorq $63, %rax
342338
; X64-NEXT: retq
343339
;

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