Revert "[DAG] Reducing instructions by better legalization handling of AVGFLOORU for illegal data types (#99913)"

This reverts commit d5521d1.

The AArch64 test is failing on the bots.

Author: topperc

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

@@ -9379,26 +9379,6 @@ SDValue TargetLowering::expandAVG(SDNode *N, SelectionDAG &DAG) const {
     }
   }
 
-  // avgflooru(lhs, rhs) -> or(lshr(add(lhs, rhs),1),shl(overflow, typesize-1))
-  if (Opc == ISD::AVGFLOORU && VT.isScalarInteger() && !isTypeLegal(VT)) {
-    SDValue UAddWithOverflow =
-        DAG.getNode(ISD::UADDO, dl, DAG.getVTList(VT, MVT::i1), {RHS, LHS});
-
-    SDValue Sum = UAddWithOverflow.getValue(0);
-    SDValue Overflow = UAddWithOverflow.getValue(1);
-
-    // Right shift the sum by 1
-    SDValue One = DAG.getShiftAmountConstant(1, VT, dl);
-    SDValue LShrVal = DAG.getNode(ISD::SRL, dl, VT, Sum, One);
-
-    SDValue ZeroExtOverflow = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Overflow);
-    SDValue OverflowShl =
-        DAG.getNode(ISD::SHL, dl, VT, ZeroExtOverflow,
-                    DAG.getConstant(VT.getScalarSizeInBits() - 1, dl, VT));
-
-    return DAG.getNode(ISD::OR, dl, VT, LShrVal, OverflowShl);
-  }
-
   // avgceils(lhs, rhs) -> sub(or(lhs,rhs),ashr(xor(lhs,rhs),1))
   // avgceilu(lhs, rhs) -> sub(or(lhs,rhs),lshr(xor(lhs,rhs),1))
   // avgfloors(lhs, rhs) -> add(and(lhs,rhs),ashr(xor(lhs,rhs),1))

llvm/test/CodeGen/AArch64/avgflooru-i128.ll

@@ -164,20 +164,18 @@ define i32 @test_ext_i32(i32 %a0, i32 %a1) nounwind {
 define i64 @test_fixed_i64(i64 %a0, i64 %a1) nounwind {
 ; RV32I-LABEL: test_fixed_i64:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    add a4, a3, a1
-; RV32I-NEXT:    add a0, a2, a0
-; RV32I-NEXT:    sltu a1, a0, a2
-; RV32I-NEXT:    add a2, a4, a1
-; RV32I-NEXT:    beq a2, a3, .LBB6_2
-; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    sltu a1, a2, a3
-; RV32I-NEXT:  .LBB6_2:
+; RV32I-NEXT:    and a4, a1, a3
+; RV32I-NEXT:    xor a1, a1, a3
+; RV32I-NEXT:    srli a3, a1, 1
+; RV32I-NEXT:    add a3, a4, a3
 ; RV32I-NEXT:    slli a1, a1, 31
-; RV32I-NEXT:    srli a3, a2, 1
-; RV32I-NEXT:    or a1, a3, a1
-; RV32I-NEXT:    slli a2, a2, 31
-; RV32I-NEXT:    srli a0, a0, 1
-; RV32I-NEXT:    or a0, a0, a2
+; RV32I-NEXT:    xor a4, a0, a2
+; RV32I-NEXT:    srli a4, a4, 1
+; RV32I-NEXT:    or a1, a4, a1
+; RV32I-NEXT:    and a2, a0, a2
+; RV32I-NEXT:    add a0, a2, a1
+; RV32I-NEXT:    sltu a1, a0, a2
+; RV32I-NEXT:    add a1, a3, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: test_fixed_i64:
@@ -197,20 +195,18 @@ define i64 @test_fixed_i64(i64 %a0, i64 %a1) nounwind {
 define i64 @test_ext_i64(i64 %a0, i64 %a1) nounwind {
 ; RV32I-LABEL: test_ext_i64:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    add a4, a3, a1
-; RV32I-NEXT:    add a0, a2, a0
-; RV32I-NEXT:    sltu a1, a0, a2
-; RV32I-NEXT:    add a2, a4, a1
-; RV32I-NEXT:    beq a2, a3, .LBB7_2
-; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    sltu a1, a2, a3
-; RV32I-NEXT:  .LBB7_2:
+; RV32I-NEXT:    and a4, a1, a3
+; RV32I-NEXT:    xor a1, a1, a3
+; RV32I-NEXT:    srli a3, a1, 1
+; RV32I-NEXT:    add a3, a4, a3
 ; RV32I-NEXT:    slli a1, a1, 31
-; RV32I-NEXT:    srli a3, a2, 1
-; RV32I-NEXT:    or a1, a3, a1
-; RV32I-NEXT:    slli a2, a2, 31
-; RV32I-NEXT:    srli a0, a0, 1
-; RV32I-NEXT:    or a0, a0, a2
+; RV32I-NEXT:    xor a4, a0, a2
+; RV32I-NEXT:    srli a4, a4, 1
+; RV32I-NEXT:    or a1, a4, a1
+; RV32I-NEXT:    and a2, a0, a2
+; RV32I-NEXT:    add a0, a2, a1
+; RV32I-NEXT:    sltu a1, a0, a2
+; RV32I-NEXT:    add a1, a3, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: test_ext_i64: