[AMDGPU] Concatenate nested namespaces. NFC.

Author: jayfoad

llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp

@@ -47,8 +47,7 @@ static cl::opt<bool> VerifyHSAMetadata(
     "amdgpu-verify-hsa-metadata",
     cl::desc("Verify AMDGPU HSA Metadata"));
 
-namespace AMDGPU {
-namespace HSAMD {
+namespace AMDGPU::HSAMD {
 
 //===----------------------------------------------------------------------===//
 // HSAMetadataStreamerV4
@@ -707,6 +706,5 @@ void MetadataStreamerMsgPackV6::emitVersion() {
   getRootMetadata("amdhsa.version") = Version;
 }
 
-} // end namespace HSAMD
-} // end namespace AMDGPU
+} // end namespace AMDGPU::HSAMD
 } // end namespace llvm

llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.cpp

@@ -18,8 +18,7 @@
 #include "llvm/MC/TargetRegistry.h"
 #include "llvm/Support/WithColor.h"
 
-namespace llvm {
-namespace mca {
+namespace llvm::mca {
 
 void AMDGPUInstrPostProcess::postProcessInstruction(
     std::unique_ptr<Instruction> &Inst, const MCInst &MCI) {
@@ -332,8 +331,7 @@ bool AMDGPUCustomBehaviour::isAlwaysGDS(uint16_t Opcode) const {
   return Opcode == AMDGPU::DS_ORDERED_COUNT || isGWS(Opcode);
 }
 
-} // namespace mca
-} // namespace llvm
+} // namespace llvm::mca
 
 using namespace llvm;
 using namespace mca;

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

@@ -40,14 +40,12 @@ using namespace llvm;
 #define GET_INSTRINFO_CTOR_DTOR
 #include "AMDGPUGenInstrInfo.inc"
 
-namespace llvm {
-namespace AMDGPU {
+namespace llvm::AMDGPU {
 #define GET_D16ImageDimIntrinsics_IMPL
 #define GET_ImageDimIntrinsicTable_IMPL
 #define GET_RsrcIntrinsics_IMPL
 #include "AMDGPUGenSearchableTables.inc"
 }
-}
 
 
 // Must be at least 4 to be able to branch over minimum unconditional branch

llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp

@@ -135,8 +135,7 @@ static const char *getReasonStr(SIScheduleCandReason Reason) {
 
 #endif
 
-namespace llvm {
-namespace SISched {
+namespace llvm::SISched {
 static bool tryLess(int TryVal, int CandVal,
                     SISchedulerCandidate &TryCand,
                     SISchedulerCandidate &Cand,
@@ -170,8 +169,7 @@ static bool tryGreater(int TryVal, int CandVal,
   Cand.setRepeat(Reason);
   return false;
 }
-} // end namespace SISched
-} // end namespace llvm
+} // end namespace llvm::SISched
 
 // SIScheduleBlock //
 

llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp

@@ -9,8 +9,7 @@
 #include "AMDGPUBaseInfo.h"
 #include "SIDefines.h"
 
-namespace llvm {
-namespace AMDGPU {
+namespace llvm::AMDGPU {
 
 //===----------------------------------------------------------------------===//
 // Custom Operands.
@@ -684,5 +683,4 @@ ArrayRef<GFXVersion> getGFXVersions() {
 
 } // namespace UCVersion
 
-} // namespace AMDGPU
-} // namespace llvm
+} // namespace llvm::AMDGPU

llvm/lib/Target/AMDGPU/Utils/AMDGPUMemoryUtils.cpp

@@ -25,9 +25,7 @@
 
 using namespace llvm;
 
-namespace llvm {
-
-namespace AMDGPU {
+namespace llvm::AMDGPU {
 
 Align getAlign(const DataLayout &DL, const GlobalVariable *GV) {
   return DL.getValueOrABITypeAlignment(GV->getPointerAlignment(DL),
@@ -371,6 +369,4 @@ bool isClobberedInFunction(const LoadInst *Load, MemorySSA *MSSA,
   return false;
 }
 
-} // end namespace AMDGPU
-
-} // end namespace llvm
+} // end namespace llvm::AMDGPU