Address review

Author: Zaara Syeda

llvm/test/CodeGen/PowerPC/toc-data-common.ll

@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple powerpc-ibm-aix-xcoff -verify-machineinstrs < %s | FileCheck %s --check-prefix CHECK
-; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -verify-machineinstrs < %s | FileCheck %s --check-prefix CHECK64
+; RUN: llc -mtriple powerpc-ibm-aix-xcoff -verify-machineinstrs < %s | FileCheck %s -DINSTR=lwz --check-prefix=CHECK
+; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -verify-machineinstrs < %s | FileCheck %s -DINSTR=ld --check-prefix=CHECK
 
 ; RUN: llc -filetype=obj -mtriple powerpc-ibm-aix-xcoff -verify-machineinstrs < %s -o %t32.o
 ; RUN: llvm-objdump -t --symbol-description %t32.o | FileCheck %s --check-prefix=OBJ32
@@ -19,24 +19,12 @@ define void @set(i32 noundef %_a) {
 ; CHECK-NEXT: la 4, a2[TD](2)
 ; CHECK-NEXT: la 5, a1[TD](2)
 ; CHECK-NEXT: stw 3, 0(4)
-; CHECK-NEXT: lwz 4, L..C0(2) # @a4
+; CHECK-NEXT: [[INSTR]] 4, L..C0(2) # @a4
 ; CHECK-NEXT: stw 3, 0(5)
-; CHECK-NEXT: lwz 5, L..C1(2) # @a3
+; CHECK-NEXT: [[INSTR]] 5, L..C1(2) # @a3
 ; CHECK-NEXT: stw 3, 0(4)
 ; CHECK-NEXT: stw 3, 0(5)
 ; CHECK-NEXT: blr
-;
-; CHECK64-LABEL: set:
-; CHECK64: # %bb.0: # %entry
-; CHECK64-NEXT: la 4, a2[TD](2)
-; CHECK64-NEXT: la 5, a1[TD](2)
-; CHECK64-NEXT: stw 3, 0(4)
-; CHECK64-NEXT: ld 4, L..C0(2) # @a4
-; CHECK64-NEXT: stw 3, 0(5)
-; CHECK64-NEXT: ld 5, L..C1(2) # @a3
-; CHECK64-NEXT: stw 3, 0(4)
-; CHECK64-NEXT: stw 3, 0(5)
-; CHECK64-NEXT: blr
 entry:
 store i32 %_a, ptr @a2, align 4
 store i32 %_a, ptr @a1, align 4
@@ -51,12 +39,6 @@ define i32 @get1() {
 ; CHECK-NEXT: la 3, a2[TD](2)
 ; CHECK-NEXT: lwz 3, 0(3)
 ; CHECK-NEXT: blr
-;
-; CHECK64-LABEL: get1:
-; CHECK64: # %bb.0: # %entry
-; CHECK64-NEXT: la 3, a2[TD](2)
-; CHECK64-NEXT: lwz 3, 0(3)
-; CHECK64-NEXT: blr
 entry:
 %0 = load i32, ptr @a2, align 4
 ret i32 %0
@@ -68,12 +50,6 @@ define i32 @get2() {
 ; CHECK-NEXT: la 3, a1[TD](2)
 ; CHECK-NEXT: lwz 3, 0(3)
 ; CHECK-NEXT: blr
-;
-; CHECK64-LABEL: get2:
-; CHECK64: # %bb.0: # %entry
-; CHECK64-NEXT: la 3, a1[TD](2)
-; CHECK64-NEXT: lwz 3, 0(3)
-; CHECK64-NEXT: blr
 entry:
 %0 = load i32, ptr @a1, align 4
 ret i32 %0
@@ -82,15 +58,9 @@ ret i32 %0
 define i32 @get3() {
 ; CHECK-LABEL: get3:
 ; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lwz 3, L..C0(2) # @a4
+; CHECK-NEXT: [[INSTR]] 3, L..C0(2) # @a4
 ; CHECK-NEXT: lwz 3, 0(3)
 ; CHECK-NEXT: blr
-;
-; CHECK64-LABEL: get3:
-; CHECK64: # %bb.0: # %entry
-; CHECK64-NEXT: ld 3, L..C0(2) # @a4
-; CHECK64-NEXT: lwz 3, 0(3)
-; CHECK64-NEXT: blr
 entry:
 %0 = load i32, ptr @a4, align 4
 ret i32 %0
@@ -99,15 +69,9 @@ ret i32 %0
 define i32 @get4() {
 ; CHECK-LABEL: get4:
 ; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lwz 3, L..C1(2) # @a3
+; CHECK-NEXT: [[INSTR]] 3, L..C1(2) # @a3
 ; CHECK-NEXT: lwz 3, 0(3)
 ; CHECK-NEXT: blr
-;
-; CHECK64-LABEL: get4:
-; CHECK64: # %bb.0: # %entry
-; CHECK64-NEXT: ld 3, L..C1(2) # @a3
-; CHECK64-NEXT: lwz 3, 0(3)
-; CHECK64-NEXT: blr
 entry:
 %0 = load i32, ptr @a3, align 4
 ret i32 %0
@@ -118,11 +82,6 @@ define nonnull ptr @escape1() {
 ; CHECK: # %bb.0: # %entry
 ; CHECK-NEXT: la 3, a2[TD](2)
 ; CHECK-NEXT: blr
-;
-; CHECK64-LABEL: escape1:
-; CHECK64: # %bb.0: # %entry
-; CHECK64-NEXT: la 3, a2[TD](2)
-; CHECK64-NEXT: blr
 entry:
 ret ptr @a2
 }
@@ -132,60 +91,45 @@ define nonnull ptr @escape2() {
 ; CHECK: # %bb.0: # %entry
 ; CHECK-NEXT: la 3, a1[TD](2)
 ; CHECK-NEXT: blr
-;
-; CHECK64-LABEL: escape2:
-; CHECK64: # %bb.0: # %entry
-; CHECK64-NEXT: la 3, a1[TD](2)
-; CHECK64-NEXT: blr
 entry:
 ret ptr @a1
 }
 
 define nonnull ptr @escape3() {
 ; CHECK-LABEL: escape3:
 ; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lwz 3, L..C0(2) # @a4
+; CHECK-NEXT: [[INSTR]] 3, L..C0(2) # @a4
 ; CHECK-NEXT: blr
-;
-; CHECK64-LABEL: escape3:
-; CHECK64: # %bb.0: # %entry
-; CHECK64-NEXT: ld 3, L..C0(2) # @a4
-; CHECK64-NEXT: blr
 entry:
 ret ptr @a4
 }
 
 define nonnull ptr @escape4() {
 ; CHECK-LABEL: escape4:
 ; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lwz 3, L..C1(2) # @a3
+; CHECK-NEXT: [[INSTR]] 3, L..C1(2) # @a3
 ; CHECK-NEXT: blr
-;
-; CHECK64-LABEL: escape4:
-; CHECK64: # %bb.0: # %entry
-; CHECK64-NEXT: ld 3, L..C1(2) # @a3
-; CHECK64-NEXT: blr
 entry:
 ret ptr @a3
 }
 
 attributes #0 = { "toc-data" }
 
-; CHECK,CHECK64: .comm a3[RW],4,2 # @a3
-; CHECK-NEXT,CHECK64-NEXT: .csect a4[RW],2
-; CHECK-NEXT,CHECK64-NEXT: .globl a4[RW] # @a4
-; CHECK-NEXT,CHECK64-NEXT: .align 2
-; CHECK-NEXT,CHECK64-NEXT: .vbyte 4, 0 # 0x0
-; CHECK-NEXT,CHECK64-NEXT: .toc
-; CHECK-LABEL,CHECK64-LABEL: L..C0:
-; CHECK-NEXT,CHECK64-NEXT: .tc a4[TC],a4[RW]
-; CHECK-LABEL,CHECK64-LABEL: L..C1:
-; CHECK-NEXT,CHECK64-NEXT: .tc a3[TC],a3[RW]
-; CHECK-NEXT,CHECK64-NEXT: .csect a2[TD],2
-; CHECK-NEXT,CHECK64-NEXT: .globl a2[TD] # @a2
-; CHECK-NEXT,CHECK64-NEXT: .align 2
-; CHECK-NEXT,CHECK64-NEXT: .vbyte 4, 0 # 0x0
-; CHECK-NEXT,CHECK64-NEXT: .comm a1[TD],4,2 # @a1
+; CHECK: .comm a3[RW],4,2 # @a3
+; CHECK-NEXT: .csect a4[RW],2
+; CHECK-NEXT: .globl a4[RW] # @a4
+; CHECK-NEXT: .align 2
+; CHECK-NEXT: .vbyte 4, 0 # 0x0
+; CHECK-NEXT: .toc
+; CHECK-LABEL: L..C0:
+; CHECK-NEXT: .tc a4[TC],a4[RW]
+; CHECK-LABEL: L..C1:
+; CHECK-NEXT: .tc a3[TC],a3[RW]
+; CHECK-NEXT: .csect a2[TD],2
+; CHECK-NEXT: .globl a2[TD] # @a2
+; CHECK-NEXT: .align 2
+; CHECK-NEXT: .vbyte 4, 0 # 0x0
+; CHECK-NEXT: .comm a1[TD],4,2 # @a1
 
 ; OBJ32:       {{([[:xdigit:]]{8})}} g     O .data  00000004 (idx: {{[0-9]+}}) a4[RW]
 ; OBJ32-LABEL: {{([[:xdigit:]]{8})}} l       .data  00000000 (idx: {{[0-9]+}}) TOC[TC0]