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[RISCV][GISel] Sink getOperandsMapping call out of the switch in getInstrMapping.
Use a SmallVector of ValueMapping * that we populate in the switch for each register operand. The entry in the SmallVector defaults to nullptr foreach operand so we don't need to do explicit nullptr in the switch. Afer this we can generically fill in GPR for registers as a default case and remove some opcodes from the switch.
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llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp

Lines changed: 56 additions & 58 deletions
Original file line numberDiff line numberDiff line change
@@ -199,12 +199,8 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
199199
const ValueMapping *GPRValueMapping =
200200
&RISCV::ValueMappings[GPRSize == 64 ? RISCV::GPRB64Idx
201201
: RISCV::GPRB32Idx];
202-
const ValueMapping *OperandsMapping = GPRValueMapping;
203202

204203
switch (Opc) {
205-
case TargetOpcode::G_INVOKE_REGION_START:
206-
OperandsMapping = getOperandsMapping({});
207-
break;
208204
case TargetOpcode::G_ADD:
209205
case TargetOpcode::G_SUB:
210206
case TargetOpcode::G_SHL:
@@ -233,14 +229,37 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
233229
case TargetOpcode::G_ZEXT:
234230
case TargetOpcode::G_SEXTLOAD:
235231
case TargetOpcode::G_ZEXTLOAD:
232+
return getInstructionMapping(DefaultMappingID, /*Cost=*/1, GPRValueMapping,
233+
NumOperands);
234+
case TargetOpcode::G_FADD:
235+
case TargetOpcode::G_FSUB:
236+
case TargetOpcode::G_FMUL:
237+
case TargetOpcode::G_FDIV:
238+
case TargetOpcode::G_FABS:
239+
case TargetOpcode::G_FNEG:
240+
case TargetOpcode::G_FSQRT:
241+
case TargetOpcode::G_FMAXNUM:
242+
case TargetOpcode::G_FMINNUM: {
243+
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
244+
return getInstructionMapping(DefaultMappingID, /*Cost=*/1,
245+
getFPValueMapping(Ty.getSizeInBits()),
246+
NumOperands);
247+
}
248+
}
249+
250+
SmallVector<const ValueMapping *, 4> OpdsMapping(NumOperands);
251+
252+
switch (Opc) {
253+
case TargetOpcode::G_INVOKE_REGION_START:
236254
break;
237255
case TargetOpcode::G_LOAD: {
238256
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
257+
OpdsMapping[0] = GPRValueMapping;
258+
OpdsMapping[1] = GPRValueMapping;
239259
// Use FPR64 for s64 loads on rv32.
240260
if (GPRSize == 32 && Ty.getSizeInBits() == 64) {
241261
assert(MF.getSubtarget<RISCVSubtarget>().hasStdExtD());
242-
OperandsMapping =
243-
getOperandsMapping({getFPValueMapping(64), GPRValueMapping});
262+
OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits());
244263
break;
245264
}
246265

@@ -254,105 +273,85 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
254273
// not, we would have had a bitcast before reaching that
255274
// instruction.
256275
return onlyUsesFP(UseMI, MRI, TRI);
257-
})) {
258-
OperandsMapping = getOperandsMapping(
259-
{getFPValueMapping(Ty.getSizeInBits()), GPRValueMapping});
260-
}
276+
}))
277+
OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits());
261278

262279
break;
263280
}
264281
case TargetOpcode::G_STORE: {
265282
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
283+
OpdsMapping[0] = GPRValueMapping;
284+
OpdsMapping[1] = GPRValueMapping;
266285
// Use FPR64 for s64 stores on rv32.
267286
if (GPRSize == 32 && Ty.getSizeInBits() == 64) {
268287
assert(MF.getSubtarget<RISCVSubtarget>().hasStdExtD());
269-
OperandsMapping =
270-
getOperandsMapping({getFPValueMapping(64), GPRValueMapping});
288+
OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits());
271289
break;
272290
}
273291

274292
MachineInstr *DefMI = MRI.getVRegDef(MI.getOperand(0).getReg());
275-
if (onlyDefinesFP(*DefMI, MRI, TRI)) {
276-
OperandsMapping = getOperandsMapping(
277-
{getFPValueMapping(Ty.getSizeInBits()), GPRValueMapping});
278-
}
293+
if (onlyDefinesFP(*DefMI, MRI, TRI))
294+
OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits());
279295
break;
280296
}
281297
case TargetOpcode::G_CONSTANT:
282298
case TargetOpcode::G_FRAME_INDEX:
283299
case TargetOpcode::G_GLOBAL_VALUE:
284300
case TargetOpcode::G_JUMP_TABLE:
285301
case TargetOpcode::G_BRCOND:
286-
OperandsMapping = getOperandsMapping({GPRValueMapping, nullptr});
302+
OpdsMapping[0] = GPRValueMapping;
287303
break;
288304
case TargetOpcode::G_BR:
289-
OperandsMapping = getOperandsMapping({nullptr});
290305
break;
291306
case TargetOpcode::G_BRJT:
292-
OperandsMapping =
293-
getOperandsMapping({GPRValueMapping, nullptr, GPRValueMapping});
307+
OpdsMapping[0] = GPRValueMapping;
308+
OpdsMapping[2] = GPRValueMapping;
294309
break;
295310
case TargetOpcode::G_ICMP:
296-
OperandsMapping = getOperandsMapping(
297-
{GPRValueMapping, nullptr, GPRValueMapping, GPRValueMapping});
311+
OpdsMapping[0] = GPRValueMapping;
312+
OpdsMapping[2] = GPRValueMapping;
313+
OpdsMapping[3] = GPRValueMapping;
298314
break;
299315
case TargetOpcode::G_SEXT_INREG:
300-
OperandsMapping =
301-
getOperandsMapping({GPRValueMapping, GPRValueMapping, nullptr});
316+
OpdsMapping[0] = GPRValueMapping;
317+
OpdsMapping[1] = GPRValueMapping;
302318
break;
303319
case TargetOpcode::G_SELECT:
304-
OperandsMapping = getOperandsMapping(
305-
{GPRValueMapping, GPRValueMapping, GPRValueMapping, GPRValueMapping});
306-
break;
307-
case TargetOpcode::G_FADD:
308-
case TargetOpcode::G_FSUB:
309-
case TargetOpcode::G_FMUL:
310-
case TargetOpcode::G_FDIV:
311-
case TargetOpcode::G_FNEG:
312-
case TargetOpcode::G_FABS:
313-
case TargetOpcode::G_FSQRT:
314-
case TargetOpcode::G_FMAXNUM:
315-
case TargetOpcode::G_FMINNUM: {
316-
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
317-
OperandsMapping = getFPValueMapping(Ty.getSizeInBits());
320+
OpdsMapping[0] = GPRValueMapping;
321+
OpdsMapping[1] = GPRValueMapping;
322+
OpdsMapping[2] = GPRValueMapping;
323+
OpdsMapping[3] = GPRValueMapping;
318324
break;
319-
}
320325
case TargetOpcode::G_FMA: {
321326
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
322-
const RegisterBankInfo::ValueMapping *FPValueMapping =
323-
getFPValueMapping(Ty.getSizeInBits());
324-
OperandsMapping = getOperandsMapping(
325-
{FPValueMapping, FPValueMapping, FPValueMapping, FPValueMapping});
327+
std::fill_n(OpdsMapping.begin(), 4, getFPValueMapping(Ty.getSizeInBits()));
326328
break;
327329
}
328330
case TargetOpcode::G_FPEXT:
329331
case TargetOpcode::G_FPTRUNC: {
330332
LLT ToTy = MRI.getType(MI.getOperand(0).getReg());
331333
LLT FromTy = MRI.getType(MI.getOperand(1).getReg());
332-
OperandsMapping =
333-
getOperandsMapping({getFPValueMapping(ToTy.getSizeInBits()),
334-
getFPValueMapping(FromTy.getSizeInBits())});
334+
OpdsMapping[0] = getFPValueMapping(ToTy.getSizeInBits());
335+
OpdsMapping[1] = getFPValueMapping(FromTy.getSizeInBits());
335336
break;
336337
}
337338
case TargetOpcode::G_FPTOSI:
338339
case TargetOpcode::G_FPTOUI: {
339340
LLT Ty = MRI.getType(MI.getOperand(1).getReg());
340-
OperandsMapping =
341-
getOperandsMapping({GPRValueMapping,
342-
getFPValueMapping(Ty.getSizeInBits())});
341+
OpdsMapping[0] = GPRValueMapping;
342+
OpdsMapping[1] = getFPValueMapping(Ty.getSizeInBits());
343343
break;
344344
}
345345
case TargetOpcode::G_SITOFP:
346346
case TargetOpcode::G_UITOFP: {
347347
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
348-
OperandsMapping = getOperandsMapping(
349-
{getFPValueMapping(Ty.getSizeInBits()), GPRValueMapping});
348+
OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits());
349+
OpdsMapping[1] = GPRValueMapping;
350350
break;
351351
}
352352
case TargetOpcode::G_FCONSTANT: {
353353
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
354-
OperandsMapping =
355-
getOperandsMapping({getFPValueMapping(Ty.getSizeInBits()), nullptr});
354+
OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits());
356355
break;
357356
}
358357
case TargetOpcode::G_FCMP: {
@@ -361,15 +360,14 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
361360
unsigned Size = Ty.getSizeInBits();
362361
assert((Size == 32 || Size == 64) && "Unsupported size for G_FCMP");
363362

364-
auto *FPRValueMapping = getFPValueMapping(Size);
365-
OperandsMapping = getOperandsMapping(
366-
{GPRValueMapping, nullptr, FPRValueMapping, FPRValueMapping});
363+
OpdsMapping[0] = GPRValueMapping;
364+
OpdsMapping[2] = OpdsMapping[3] = getFPValueMapping(Size);
367365
break;
368366
}
369367
default:
370368
return getInvalidInstructionMapping();
371369
}
372370

373-
return getInstructionMapping(DefaultMappingID, /*Cost=*/1, OperandsMapping,
374-
NumOperands);
371+
return getInstructionMapping(DefaultMappingID, /*Cost=*/1,
372+
getOperandsMapping(OpdsMapping), NumOperands);
375373
}

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