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[RISCV] Add back missing vmv_v_x_vl pattern predicates #101455

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Merged
merged 1 commit into from
Aug 1, 2024

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lukel97
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@lukel97 lukel97 commented Aug 1, 2024

Looks like these got left behind in 17e2d07

I tried to create a test case by adding run lines for +zvl32x,+zvl128b in the existing splat tests but they crashed for a separate reason:

WidenVectorResult #0: t8: nxv1i8 = llvm.riscv.vmv.v.x TargetConstant:i64<10683>, undef:nxv1i8, t5, t4

LLVM ERROR: Do not know how to widen the result of this operator!

Looks like these got left behind in 17e2d07

I tried to create a test case by adding run lines for +zvl32x,+zvl128b in the existing splat tests but they crashed for a separate reason:

    WidenVectorResult #0: t8: nxv1i8 = llvm.riscv.vmv.v.x TargetConstant:i64<10683>, undef:nxv1i8, t5, t4

    LLVM ERROR: Do not know how to widen the result of this operator!
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llvmbot commented Aug 1, 2024

@llvm/pr-subscribers-backend-risc-v

Author: Luke Lau (lukel97)

Changes

Looks like these got left behind in 17e2d07

I tried to create a test case by adding run lines for +zvl32x,+zvl128b in the existing splat tests but they crashed for a separate reason:

WidenVectorResult #<!-- -->0: t8: nxv1i8 = llvm.riscv.vmv.v.x TargetConstant:i64&lt;10683&gt;, undef:nxv1i8, t5, t4

LLVM ERROR: Do not know how to widen the result of this operator!

Full diff: https://github.com/llvm/llvm-project/pull/101455.diff

1 Files Affected:

  • (modified) llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td (+10-8)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index 394da8040a13e..699536b186969 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -2369,14 +2369,16 @@ foreach vti = AllVectors in {
 }
 
 foreach vti = AllIntegerVectors in {
-    def : Pat<(vti.Vector (riscv_vmv_v_x_vl vti.RegClass:$passthru, GPR:$rs2, VLOpFrag)),
-              (!cast<Instruction>("PseudoVMV_V_X_"#vti.LMul.MX)
-               vti.RegClass:$passthru, GPR:$rs2, GPR:$vl, vti.Log2SEW, TU_MU)>;
-    defvar ImmPat = !cast<ComplexPattern>("sew"#vti.SEW#"simm5");
-    def : Pat<(vti.Vector (riscv_vmv_v_x_vl vti.RegClass:$passthru, (ImmPat simm5:$imm5),
-                                                VLOpFrag)),
-              (!cast<Instruction>("PseudoVMV_V_I_"#vti.LMul.MX)
-               vti.RegClass:$passthru, simm5:$imm5, GPR:$vl, vti.Log2SEW, TU_MU)>;
+  let Predicates = GetVTypePredicates<vti>.Predicates in {
+      def : Pat<(vti.Vector (riscv_vmv_v_x_vl vti.RegClass:$passthru, GPR:$rs2, VLOpFrag)),
+                (!cast<Instruction>("PseudoVMV_V_X_"#vti.LMul.MX)
+                 vti.RegClass:$passthru, GPR:$rs2, GPR:$vl, vti.Log2SEW, TU_MU)>;
+      defvar ImmPat = !cast<ComplexPattern>("sew"#vti.SEW#"simm5");
+      def : Pat<(vti.Vector (riscv_vmv_v_x_vl vti.RegClass:$passthru, (ImmPat simm5:$imm5),
+                                                  VLOpFrag)),
+                (!cast<Instruction>("PseudoVMV_V_I_"#vti.LMul.MX)
+                 vti.RegClass:$passthru, simm5:$imm5, GPR:$vl, vti.Log2SEW, TU_MU)>;
+    }
   }
 }
 

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LGTM. Nice catch!

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@topperc topperc left a comment

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LGTM

@lukel97 lukel97 merged commit fdce0bf into llvm:main Aug 1, 2024
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4 participants