[RISCV] Assign different scheduling classes for VMADC/VMSBC #113009
Merged
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Split the scheduling classes of VMADC/VMSBC away from that of VADC/VSBC. Because the former are technically mask-producing instructions rather than normal vector arithmetics, which might have different performance characteristics on some processors. This is effectively NFC.
|
@llvm/pr-subscribers-backend-risc-v Author: Min-Yih Hsu (mshockwave) ChangesSplit the scheduling classes of VMADC/VMSBC away from that of VADC/VSBC. Because the former are technically mask-producing instructions rather than normal vector arithmetics, which might have different performance characteristics on some processors. This is effectively NFC. Full diff: https://github.com/llvm/llvm-project/pull/113009.diff 6 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index 6f7d14d5503bd3..f83c9485f1e33d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -630,31 +630,43 @@ multiclass VMRG_IV_V_X_I<string opcodestr, bits<6> funct6> {
}
multiclass VALUm_IV_V_X<string opcodestr, bits<6> funct6> {
+ // if LSB of funct6 is 1, it's a mask-producing instruction that
+ // uses a different scheduling class.
+ defvar WritePrefix = !if(funct6{0}, "WriteVICALUM", "WriteVICALU");
def VM : VALUmVV<funct6, OPIVV, opcodestr # ".vvm">,
- SchedBinaryMC<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV">;
+ SchedBinaryMC<WritePrefix#"V", "ReadVICALUV", "ReadVICALUV">;
def XM : VALUmVX<funct6, OPIVX, opcodestr # ".vxm">,
- SchedBinaryMC<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX">;
+ SchedBinaryMC<WritePrefix#"X", "ReadVICALUV", "ReadVICALUX">;
}
multiclass VALUm_IV_V_X_I<string opcodestr, bits<6> funct6>
: VALUm_IV_V_X<opcodestr, funct6> {
+ // if LSB of funct6 is 1, it's a mask-producing instruction that
+ // uses a different scheduling class.
+ defvar WriteSched = !if(funct6{0}, "WriteVICALUMI", "WriteVICALUI");
def IM : VALUmVI<funct6, opcodestr # ".vim">,
- SchedUnaryMC<"WriteVICALUI", "ReadVICALUV">;
+ SchedUnaryMC<WriteSched, "ReadVICALUV">;
}
multiclass VALUNoVm_IV_V_X<string opcodestr, bits<6> funct6> {
+ // if LSB of funct6 is 1, it's a mask-producing instruction that
+ // uses a different scheduling class.
+ defvar WritePrefix = !if(funct6{0}, "WriteVICALUM", "WriteVICALU");
def V : VALUVVNoVm<funct6, OPIVV, opcodestr # ".vv">,
- SchedBinaryMC<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV",
+ SchedBinaryMC<WritePrefix#"V", "ReadVICALUV", "ReadVICALUV",
forceMasked=0>;
def X : VALUVXNoVm<funct6, OPIVX, opcodestr # ".vx">,
- SchedBinaryMC<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX",
+ SchedBinaryMC<WritePrefix#"X", "ReadVICALUV", "ReadVICALUX",
forceMasked=0>;
}
multiclass VALUNoVm_IV_V_X_I<string opcodestr, bits<6> funct6>
: VALUNoVm_IV_V_X<opcodestr, funct6> {
+ // if LSB of funct6 is 1, it's a mask-producing instruction that
+ // uses a different scheduling class.
+ defvar WriteSched = !if(funct6{0}, "WriteVICALUMI", "WriteVICALUI");
def I : VALUVINoVm<funct6, opcodestr # ".vi">,
- SchedUnaryMC<"WriteVICALUI", "ReadVICALUV", forceMasked=0>;
+ SchedUnaryMC<WriteSched, "ReadVICALUV", forceMasked=0>;
}
multiclass VALU_FV_F<string opcodestr, bits<6> funct6> {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 6b308bc8c9aa0f..af4f653f57afd5 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -3072,13 +3072,13 @@ multiclass VPseudoVCALUM_VM_XM_IM {
defvar mx = m.MX;
defm "" : VPseudoBinaryV_VM<m, CarryOut=1, CarryIn=1, Constraint=constraint,
Commutable=1, TargetConstraintType=2>,
- SchedBinary<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV", mx, forceMasked=1,
+ SchedBinary<"WriteVICALUMV", "ReadVICALUV", "ReadVICALUV", mx, forceMasked=1,
forcePassthruRead=true>;
defm "" : VPseudoBinaryV_XM<m, CarryOut=1, CarryIn=1, Constraint=constraint, TargetConstraintType=2>,
- SchedBinary<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX", mx, forceMasked=1,
+ SchedBinary<"WriteVICALUMX", "ReadVICALUV", "ReadVICALUX", mx, forceMasked=1,
forcePassthruRead=true>;
defm "" : VPseudoBinaryV_IM<m, CarryOut=1, CarryIn=1, Constraint=constraint, TargetConstraintType=2>,
- SchedUnary<"WriteVICALUI", "ReadVICALUV", mx, forceMasked=1,
+ SchedUnary<"WriteVICALUMI", "ReadVICALUV", mx, forceMasked=1,
forcePassthruRead=true>;
}
}
@@ -3089,11 +3089,11 @@ multiclass VPseudoVCALUM_VM_XM {
defvar mx = m.MX;
defm "" : VPseudoBinaryV_VM<m, CarryOut=1, CarryIn=1, Constraint=constraint,
TargetConstraintType=2>,
- SchedBinary<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV", mx, forceMasked=1,
+ SchedBinary<"WriteVICALUMV", "ReadVICALUV", "ReadVICALUV", mx, forceMasked=1,
forcePassthruRead=true>;
defm "" : VPseudoBinaryV_XM<m, CarryOut=1, CarryIn=1, Constraint=constraint,
TargetConstraintType=2>,
- SchedBinary<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX", mx, forceMasked=1,
+ SchedBinary<"WriteVICALUMX", "ReadVICALUV", "ReadVICALUX", mx, forceMasked=1,
forcePassthruRead=true>;
}
}
@@ -3104,13 +3104,13 @@ multiclass VPseudoVCALUM_V_X_I {
defvar mx = m.MX;
defm "" : VPseudoBinaryV_VM<m, CarryOut=1, CarryIn=0, Constraint=constraint,
Commutable=1, TargetConstraintType=2>,
- SchedBinary<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV", mx,
+ SchedBinary<"WriteVICALUMV", "ReadVICALUV", "ReadVICALUV", mx,
forcePassthruRead=true>;
defm "" : VPseudoBinaryV_XM<m, CarryOut=1, CarryIn=0, Constraint=constraint, TargetConstraintType=2>,
- SchedBinary<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX", mx,
+ SchedBinary<"WriteVICALUMX", "ReadVICALUV", "ReadVICALUX", mx,
forcePassthruRead=true>;
defm "" : VPseudoBinaryV_IM<m, CarryOut=1, CarryIn=0, Constraint=constraint>,
- SchedUnary<"WriteVICALUI", "ReadVICALUV", mx,
+ SchedUnary<"WriteVICALUMI", "ReadVICALUV", mx,
forcePassthruRead=true>;
}
}
@@ -3120,10 +3120,10 @@ multiclass VPseudoVCALUM_V_X {
foreach m = MxList in {
defvar mx = m.MX;
defm "" : VPseudoBinaryV_VM<m, CarryOut=1, CarryIn=0, Constraint=constraint, TargetConstraintType=2>,
- SchedBinary<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV", mx,
+ SchedBinary<"WriteVICALUMV", "ReadVICALUV", "ReadVICALUV", mx,
forcePassthruRead=true>;
defm "" : VPseudoBinaryV_XM<m, CarryOut=1, CarryIn=0, Constraint=constraint, TargetConstraintType=2>,
- SchedBinary<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX", mx,
+ SchedBinary<"WriteVICALUMX", "ReadVICALUV", "ReadVICALUX", mx,
forcePassthruRead=true>;
}
}
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index 24cbe1531c017c..d07ee393bbcfd0 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -631,6 +631,9 @@ foreach mx = SchedMxList in {
defm "" : LMULWriteResMX<"WriteVICALUV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVICALUX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVICALUI", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUMV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUMX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUMI", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVShiftV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVShiftX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVShiftI", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
index 6926184e92399c..7a54d2fe108080 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
@@ -467,6 +467,9 @@ foreach mx = SchedMxList in {
defm "" : LMULWriteResMX<"WriteVICALUV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVICALUX", [SiFiveP400VEXQ0], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVICALUI", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUMV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUMX", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUMI", [SiFiveP400VEXQ0], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVICmpV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVICmpX", [SiFiveP400VEXQ0], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVICmpI", [SiFiveP400VEXQ0], mx, IsWorstCase>;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
index 59972d781a315a..c685a6d2b094be 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
@@ -403,6 +403,9 @@ foreach mx = SchedMxList in {
defm "" : LMULWriteResMX<"WriteVICALUV", [SiFiveP600VectorArith], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVICALUX", [SiFiveP600VectorArith], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVICALUI", [SiFiveP600VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUMV", [SiFiveP600VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUMX", [SiFiveP600VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUMI", [SiFiveP600VectorArith], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVICmpV", [SiFiveP600VectorArith], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVICmpX", [SiFiveP600VectorArith], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVICmpI", [SiFiveP600VectorArith], mx, IsWorstCase>;
diff --git a/llvm/lib/Target/RISCV/RISCVScheduleV.td b/llvm/lib/Target/RISCV/RISCVScheduleV.td
index ee041ea142b94c..6b9f1dd3218913 100644
--- a/llvm/lib/Target/RISCV/RISCVScheduleV.td
+++ b/llvm/lib/Target/RISCV/RISCVScheduleV.td
@@ -364,6 +364,9 @@ defm "" : LMULSchedWrites<"WriteVExtV">;
defm "" : LMULSchedWrites<"WriteVICALUV">;
defm "" : LMULSchedWrites<"WriteVICALUX">;
defm "" : LMULSchedWrites<"WriteVICALUI">;
+defm "" : LMULSchedWrites<"WriteVICALUMV">;
+defm "" : LMULSchedWrites<"WriteVICALUMX">;
+defm "" : LMULSchedWrites<"WriteVICALUMI">;
// 11.6. Vector Single-Width Bit Shift Instructions
defm "" : LMULSchedWrites<"WriteVShiftV">;
defm "" : LMULSchedWrites<"WriteVShiftX">;
@@ -856,6 +859,9 @@ defm "" : LMULWriteRes<"WriteVExtV", []>;
defm "" : LMULWriteRes<"WriteVICALUV", []>;
defm "" : LMULWriteRes<"WriteVICALUX", []>;
defm "" : LMULWriteRes<"WriteVICALUI", []>;
+defm "" : LMULWriteRes<"WriteVICALUMV", []>;
+defm "" : LMULWriteRes<"WriteVICALUMX", []>;
+defm "" : LMULWriteRes<"WriteVICALUMI", []>;
defm "" : LMULWriteRes<"WriteVShiftV", []>;
defm "" : LMULWriteRes<"WriteVShiftX", []>;
defm "" : LMULWriteRes<"WriteVShiftI", []>;
|
wangpc-pp
reviewed
Oct 21, 2024
NoumanAmir657
pushed a commit
to NoumanAmir657/llvm-project
that referenced
this pull request
Nov 4, 2024
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Split the scheduling classes of VMADC/VMSBC away from that of VADC/VSBC. Because the former are technically mask-producing instructions rather than normal vector arithmetics, which might have different performance characteristics on some processors.
This is effectively NFC.