Skip to content

[RISCV][GISel] Add isel patterns for i16 load/store #116293

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Nov 16, 2024
Merged

[RISCV][GISel] Add isel patterns for i16 load/store #116293

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
17 changes: 11 additions & 6 deletions llvm/lib/Target/RISCV/RISCVGISel.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -169,6 +169,11 @@ def : LdPat<load, LD, PtrVT>;
def : StPat<store, SD, GPR, PtrVT>;
}

// Load and store patterns for i16, needed because Zfh makes s16 load/store
// legal and regbank select may not constrain registers to FP.
def : LdPat<load, LH, i16>;
def : StPat<store, SH, GPR, i16>;

//===----------------------------------------------------------------------===//
// RV64 i32 patterns not used by SelectionDAG
//===----------------------------------------------------------------------===//
Expand All @@ -187,22 +192,22 @@ def : LdPat<extloadi16, LH, i32>;
def : StPat<truncstorei8, SB, GPR, i32>;
def : StPat<truncstorei16, SH, GPR, i32>;

def : Pat<(anyext GPR:$src), (COPY GPR:$src)>;
def : Pat<(sext GPR:$src), (ADDIW GPR:$src, 0)>;
def : Pat<(trunc GPR:$src), (COPY GPR:$src)>;
def : Pat<(anyext (i32 GPR:$src)), (COPY GPR:$src)>;
def : Pat<(sext (i32 GPR:$src)), (ADDIW GPR:$src, 0)>;
def : Pat<(i32 (trunc GPR:$src)), (COPY GPR:$src)>;

// Use sext if the sign bit of the input is 0.
def : Pat<(zext_is_sext GPR:$src), (ADDIW GPR:$src, 0)>;
def : Pat<(zext_is_sext (i32 GPR:$src)), (ADDIW GPR:$src, 0)>;
}

let Predicates = [IsRV64, NotHasStdExtZba] in {
def : Pat<(zext GPR:$src), (SRLI (i64 (SLLI GPR:$src, 32)), 32)>;
def : Pat<(zext (i32 GPR:$src)), (SRLI (i64 (SLLI GPR:$src, 32)), 32)>;
}

//===----------------------------------------------------------------------===//
// Zb* RV64 i32 patterns not used by SelectionDAG.
//===----------------------------------------------------------------------===//

let Predicates = [HasStdExtZba, IsRV64] in {
def : Pat<(zext GPR:$src), (ADD_UW GPR:$src, (XLenVT X0))>;
def : Pat<(zext (i32 GPR:$src)), (ADD_UW GPR:$src, (XLenVT X0))>;
}
2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/RISCVRegisterInfo.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -231,7 +231,7 @@ class RISCVRegisterClass<list<ValueType> regTypes, int align, dag regList>
}

class GPRRegisterClass<dag regList>
: RISCVRegisterClass<[XLenVT, XLenFVT, i32], 32, regList> {
: RISCVRegisterClass<[XLenVT, XLenFVT, i32, i16], 32, regList> {
let RegInfos = XLenRI;
}

Expand Down
25 changes: 24 additions & 1 deletion llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv32.mir
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=instruction-select %s -o - \
# RUN: | FileCheck %s
# RUN: -disable-gisel-legality-check | FileCheck %s

---
name: load_i8
Expand Down Expand Up @@ -45,6 +45,29 @@ body: |
$x10 = COPY %1(s32)
PseudoRET implicit $x10

...
---
name: load_i16_i16
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $x10

; CHECK-LABEL: name: load_i16_i16
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[LH:%[0-9]+]]:gpr = LH [[COPY]], 0 :: (load (s16))
; CHECK-NEXT: $x10 = COPY [[LH]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:gprb(p0) = COPY $x10
%1:gprb(s16) = G_LOAD %0(p0) :: (load (s16))
%2:gprb(s32) = G_ANYEXT %1
$x10 = COPY %2(s32)
PseudoRET implicit $x10

...
---
name: load_i32
Expand Down
25 changes: 24 additions & 1 deletion llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -run-pass=instruction-select %s -o - \
# RUN: | FileCheck %s
# RUN: -disable-gisel-legality-check | FileCheck %s

---
name: load_i8_i64
Expand Down Expand Up @@ -45,6 +45,29 @@ body: |
$x10 = COPY %1(s64)
PseudoRET implicit $x10

...
---
name: load_i16_i16
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $x10

; CHECK-LABEL: name: load_i16_i16
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[LH:%[0-9]+]]:gpr = LH [[COPY]], 0 :: (load (s16))
; CHECK-NEXT: $x10 = COPY [[LH]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:gprb(p0) = COPY $x10
%1:gprb(s16) = G_LOAD %0(p0) :: (load (s16))
%2:gprb(s64) = G_ANYEXT %1
$x10 = COPY %2(s64)
PseudoRET implicit $x10

...
---
name: load_i32_i64
Expand Down
25 changes: 24 additions & 1 deletion llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv32.mir
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=instruction-select %s -o - \
# RUN: | FileCheck %s
# RUN: -disable-gisel-legality-check | FileCheck %s
#
---
name: store_i8
Expand Down Expand Up @@ -45,6 +45,29 @@ body: |
G_STORE %0(s32), %1(p0) :: (store (s16))
PseudoRET

...
---
name: store_i16_i16
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $x10, $x11

; CHECK-LABEL: name: store_i16_i16
; CHECK: liveins: $x10, $x11
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
; CHECK-NEXT: SH [[COPY]], [[COPY1]], 0 :: (store (s16))
; CHECK-NEXT: PseudoRET
%0:gprb(s32) = COPY $x10
%1:gprb(p0) = COPY $x11
%2:gprb(s16) = G_TRUNC %0
G_STORE %2(s16), %1(p0) :: (store (s16))
PseudoRET

...
---
name: store_i32
Expand Down
25 changes: 24 additions & 1 deletion llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv64.mir
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -run-pass=instruction-select %s -o - \
# RUN: | FileCheck %s
# RUN: -disable-gisel-legality-check | FileCheck %s

---
name: store_i8_i64
Expand Down Expand Up @@ -45,6 +45,29 @@ body: |
G_STORE %0(s64), %1(p0) :: (store (s16))
PseudoRET

...
---
name: store_i16_i16
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $x10, $x11

; CHECK-LABEL: name: store_i16_i16
; CHECK: liveins: $x10, $x11
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
; CHECK-NEXT: SH [[COPY]], [[COPY1]], 0 :: (store (s16))
; CHECK-NEXT: PseudoRET
%0:gprb(s64) = COPY $x10
%1:gprb(p0) = COPY $x11
%2:gprb(s16) = G_TRUNC %0
G_STORE %2(s16), %1(p0) :: (store (s16))
PseudoRET

...
---
name: store_i32_i64
Expand Down
Loading