Reland "[X86] Support -march=diamondrapids (#113881)" #116564

FreddyLeaf · 2024-11-18T01:10:06Z

Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368

llvmbot · 2024-11-18T01:10:38Z

@llvm/pr-subscribers-backend-x86

@llvm/pr-subscribers-clang-driver

Author: Freddy Ye (FreddyLeaf)

Changes

Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368

Patch is 20.50 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/116564.diff

16 Files Affected:

(modified) clang/docs/ReleaseNotes.rst (+2)
(modified) clang/lib/Basic/Targets/X86.cpp (+2)
(modified) clang/test/CodeGen/attr-cpuspecific-cpus.c (+1)
(modified) clang/test/CodeGen/attr-target-mv.c (+1)
(modified) clang/test/CodeGen/target-builtin-noerror.c (+1)
(modified) clang/test/Driver/x86-march.c (+4)
(modified) clang/test/Misc/target-invalid-cpu-note/x86.c (+4)
(modified) clang/test/Preprocessor/predefined-arch-macros.c (+54)
(modified) compiler-rt/lib/builtins/cpu_model/x86.c (+14)
(modified) llvm/docs/ReleaseNotes.md (+2)
(modified) llvm/include/llvm/TargetParser/X86TargetParser.def (+1)
(modified) llvm/include/llvm/TargetParser/X86TargetParser.h (+1)
(modified) llvm/lib/Target/X86/X86.td (+29)
(modified) llvm/lib/TargetParser/Host.cpp (+13)
(modified) llvm/lib/TargetParser/X86TargetParser.cpp (+10)
(modified) llvm/test/CodeGen/X86/cpus-intel.ll (+2)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index a8830a5658c7da..044f62e770a7a0 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -769,6 +769,8 @@ X86 Support
 - Support ISA of ``AMX-TF32``.
 - Support ISA of ``MOVRS``.
 
+- Supported ``-march/tune=diamondrapids``
+
 Arm and AArch64 Support
 ^^^^^^^^^^^^^^^^^^^^^^^
 
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index 086b4415412e67..5993257e27d5a9 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -667,6 +667,7 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
   case CK_GraniterapidsD:
   case CK_Emeraldrapids:
   case CK_Clearwaterforest:
+  case CK_Diamondrapids:
     // FIXME: Historically, we defined this legacy name, it would be nice to
     // remove it at some point. We've never exposed fine-grained names for
     // recent primary x86 CPUs, and we should keep it that way.
@@ -1651,6 +1652,7 @@ std::optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const {
     case CK_GraniterapidsD:
     case CK_Emeraldrapids:
     case CK_Clearwaterforest:
+    case CK_Diamondrapids:
     case CK_KNL:
     case CK_KNM:
     // K7
diff --git a/clang/test/CodeGen/attr-cpuspecific-cpus.c b/clang/test/CodeGen/attr-cpuspecific-cpus.c
index dd154fd227b25b..1dd095ec9e191f 100644
--- a/clang/test/CodeGen/attr-cpuspecific-cpus.c
+++ b/clang/test/CodeGen/attr-cpuspecific-cpus.c
@@ -43,6 +43,7 @@ ATTR(cpu_specific(icelake_client)) void CPU(void){}
 ATTR(cpu_specific(tigerlake)) void CPU(void){}
 ATTR(cpu_specific(alderlake)) void CPU(void){}
 ATTR(cpu_specific(sapphirerapids)) void CPU(void){}
+ATTR(cpu_specific(diamondrapids)) void CPU(void){}
 
 // ALIAS CPUs
 ATTR(cpu_specific(pentium_iii_no_xmm_regs)) void CPU0(void){}
diff --git a/clang/test/CodeGen/attr-target-mv.c b/clang/test/CodeGen/attr-target-mv.c
index 2c4b95ca04370a..6911b55203b7e7 100644
--- a/clang/test/CodeGen/attr-target-mv.c
+++ b/clang/test/CodeGen/attr-target-mv.c
@@ -29,6 +29,7 @@ int __attribute__((target("arch=lunarlake"))) foo(void) {return 23;}
 int __attribute__((target("arch=gracemont"))) foo(void) {return 24;}
 int __attribute__((target("arch=pantherlake"))) foo(void) {return 25;}
 int __attribute__((target("arch=clearwaterforest"))) foo(void) {return 26;}
+int __attribute__((target("arch=diamondrapids"))) foo(void) {return 27;}
 int __attribute__((target("default"))) foo(void) { return 2; }
 
 int bar(void) {
diff --git a/clang/test/CodeGen/target-builtin-noerror.c b/clang/test/CodeGen/target-builtin-noerror.c
index 1e53621bc6b5ae..0bbd8c3e5ddd81 100644
--- a/clang/test/CodeGen/target-builtin-noerror.c
+++ b/clang/test/CodeGen/target-builtin-noerror.c
@@ -209,4 +209,5 @@ void verifycpustrings(void) {
   (void)__builtin_cpu_is("znver3");
   (void)__builtin_cpu_is("znver4");
   (void)__builtin_cpu_is("znver5");
+  (void)__builtin_cpu_is("diamondrapids");
 }
diff --git a/clang/test/Driver/x86-march.c b/clang/test/Driver/x86-march.c
index 3bc2a82ae778d6..341f01c8d668df 100644
--- a/clang/test/Driver/x86-march.c
+++ b/clang/test/Driver/x86-march.c
@@ -120,6 +120,10 @@
 // RUN:   | FileCheck %s -check-prefix=clearwaterforest
 // clearwaterforest: "-target-cpu" "clearwaterforest"
 //
+// RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=diamondrapids 2>&1 \
+// RUN:   | FileCheck %s -check-prefix=diamondrapids
+// diamondrapids: "-target-cpu" "diamondrapids"
+//
 // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=lakemont 2>&1 \
 // RUN:   | FileCheck %s -check-prefix=lakemont
 // lakemont: "-target-cpu" "lakemont"
diff --git a/clang/test/Misc/target-invalid-cpu-note/x86.c b/clang/test/Misc/target-invalid-cpu-note/x86.c
index 7879676040af46..f89cdc2aa573ff 100644
--- a/clang/test/Misc/target-invalid-cpu-note/x86.c
+++ b/clang/test/Misc/target-invalid-cpu-note/x86.c
@@ -69,6 +69,7 @@
 // X86-SAME: {{^}}, graniterapids-d
 // X86-SAME: {{^}}, emeraldrapids
 // X86-SAME: {{^}}, clearwaterforest
+// X86-SAME: {{^}}, diamondrapids
 // X86-SAME: {{^}}, knl
 // X86-SAME: {{^}}, knm
 // X86-SAME: {{^}}, lakemont
@@ -155,6 +156,7 @@
 // X86_64-SAME: {{^}}, graniterapids-d
 // X86_64-SAME: {{^}}, emeraldrapids
 // X86_64-SAME: {{^}}, clearwaterforest
+// X86_64-SAME: {{^}}, diamondrapids
 // X86_64-SAME: {{^}}, knl
 // X86_64-SAME: {{^}}, knm
 // X86_64-SAME: {{^}}, k8
@@ -250,6 +252,7 @@
 // TUNE_X86-SAME: {{^}}, graniterapids-d
 // TUNE_X86-SAME: {{^}}, emeraldrapids
 // TUNE_X86-SAME: {{^}}, clearwaterforest
+// TUNE_X86-SAME: {{^}}, diamondrapids
 // TUNE_X86-SAME: {{^}}, knl
 // TUNE_X86-SAME: {{^}}, knm
 // TUNE_X86-SAME: {{^}}, lakemont
@@ -352,6 +355,7 @@
 // TUNE_X86_64-SAME: {{^}}, graniterapids-d
 // TUNE_X86_64-SAME: {{^}}, emeraldrapids
 // TUNE_X86_64-SAME: {{^}}, clearwaterforest
+// TUNE_X86_64-SAME: {{^}}, diamondrapids
 // TUNE_X86_64-SAME: {{^}}, knl
 // TUNE_X86_64-SAME: {{^}}, knm
 // TUNE_X86_64-SAME: {{^}}, lakemont
diff --git a/clang/test/Preprocessor/predefined-arch-macros.c b/clang/test/Preprocessor/predefined-arch-macros.c
index 35801e758cc58a..20aa2d4e0a54cb 100644
--- a/clang/test/Preprocessor/predefined-arch-macros.c
+++ b/clang/test/Preprocessor/predefined-arch-macros.c
@@ -1867,13 +1867,23 @@
 // RUN: %clang -march=graniterapids-d -m32 -E -dM %s -o - 2>&1 \
 // RUN:     --target=i386 \
 // RUN:   | FileCheck -match-full-lines %s -check-prefixes=CHECK_GNR_M32,CHECK_GNRD_M32
+// RUN: %clang -march=diamondrapids -m32 -E -dM %s -o - 2>&1 \
+// RUN:     --target=i386 \
+// RUN:   | FileCheck -match-full-lines %s -check-prefixes=CHECK_GNR_M32,CHECK_GNRD_M32,CHECK_DMR_M32
 // CHECK_GNR_M32: #define __AES__ 1
+// CHECK_DMR_M32: #define __AMX_AVX512__ 1
 // CHECK_GNR_M32: #define __AMX_BF16__ 1
 // CHECK_GNR_M32-NOT: #define __AMX_COMPLEX__ 1
 // CHECK_GNRD_M32: #define __AMX_COMPLEX__ 1
 // CHECK_GNR_M32: #define __AMX_FP16__ 1
+// CHECK_DMR_M32: #define __AMX_FP8__ 1
 // CHECK_GNR_M32: #define __AMX_INT8__ 1
+// CHECK_DMR_M32: #define __AMX_MOVRS__ 1
+// CHECK_DMR_M32: #define __AMX_TF32__ 1
 // CHECK_GNR_M32: #define __AMX_TILE__ 1
+// CHECK_DMR_M32: #define __AMX_TRANSPOSE__ 1
+// CHECK_DMR_M32: #define __AVX10_2_512__ 1
+// CHECK_DMR_M32: #define __AVX10_2__ 1
 // CHECK_GNR_M32: #define __AVX2__ 1
 // CHECK_GNR_M32: #define __AVX512BF16__ 1
 // CHECK_GNR_M32: #define __AVX512BITALG__ 1
@@ -1888,13 +1898,21 @@
 // CHECK_GNR_M32: #define __AVX512VL__ 1
 // CHECK_GNR_M32: #define __AVX512VNNI__ 1
 // CHECK_GNR_M32: #define __AVX512VPOPCNTDQ__ 1
+// CHECK_DMR_M32: #define __AVXIFMA__ 1
+// CHECK_DMR_M32: #define __AVXNECONVERT__ 1
+// CHECK_DMR_M32: #define __AVXVNNIINT16__ 1
+// CHECK_DMR_M32: #define __AVXVNNIINT8__ 1
 // CHECK_GNR_M32: #define __AVXVNNI__ 1
 // CHECK_GNR_M32: #define __AVX__ 1
 // CHECK_GNR_M32: #define __BMI2__ 1
 // CHECK_GNR_M32: #define __BMI__ 1
+// CHECK_DMR_M32: #define __CCMP__ 1
+// CHECK_DMR_M32: #define __CF__ 1
 // CHECK_GNR_M32: #define __CLDEMOTE__ 1
 // CHECK_GNR_M32: #define __CLFLUSHOPT__ 1
 // CHECK_GNR_M32: #define __CLWB__ 1
+// CHECK_DMR_M32: #define __CMPCCXADD__ 1
+// CHECK_DMR_M32: #define __EGPR__ 1
 // CHECK_GNR_M32: #define __ENQCMD__ 1
 // CHECK_GNR_M32: #define __EVEX256__ 1
 // CHECK_GNR_M32: #define __EVEX512__ 1
@@ -1905,20 +1923,28 @@
 // CHECK_GNR_M32: #define __LZCNT__ 1
 // CHECK_GNR_M32: #define __MMX__ 1
 // CHECK_GNR_M32: #define __MOVBE__ 1
+// CHECK_DMR_M32: #define __MOVRS__ 1
+// CHECK_DMR_M32: #define __NDD__ 1
+// CHECK_DMR_M32: #define __NF__ 1
 // CHECK_GNR_M32: #define __PCLMUL__ 1
 // CHECK_GNR_M32: #define __PCONFIG__ 1
 // CHECK_GNR_M32: #define __PKU__ 1
 // CHECK_GNR_M32: #define __POPCNT__ 1
+// CHECK_DMR_M32: #define __PPX__ 1
 // CHECK_GNR_M32: #define __PREFETCHI__ 1
 // CHECK_GNR_M32: #define __PRFCHW__ 1
 // CHECK_GNR_M32: #define __PTWRITE__ 1
+// CHECK_DMR_M32: #define __PUSH2POP2__ 1
 // CHECK_GNR_M32: #define __RDPID__ 1
 // CHECK_GNR_M32: #define __RDRND__ 1
 // CHECK_GNR_M32: #define __RDSEED__ 1
 // CHECK_GNR_M32: #define __SERIALIZE__ 1
 // CHECK_GNR_M32: #define __SGX__ 1
+// CHECK_DMR_M32: #define __SHA512__ 1
 // CHECK_GNR_M32: #define __SHA__ 1
 // CHECK_GNR_M32: #define __SHSTK__ 1
+// CHECK_DMR_M32: #define __SM3__ 1
+// CHECK_DMR_M32: #define __SM4__ 1
 // CHECK_GNR_M32: #define __SSE2__ 1
 // CHECK_GNR_M32: #define __SSE3__ 1
 // CHECK_GNR_M32: #define __SSE4_1__ 1
@@ -1935,6 +1961,7 @@
 // CHECK_GNR_M32: #define __XSAVEOPT__ 1
 // CHECK_GNR_M32: #define __XSAVES__ 1
 // CHECK_GNR_M32: #define __XSAVE__ 1
+// CHECK_DMR_M32: #define __ZU__ 1
 // CHECK_GNR_M32: #define __corei7 1
 // CHECK_GNR_M32: #define __corei7__ 1
 // CHECK_GNR_M32: #define __i386 1
@@ -1948,13 +1975,23 @@
 // RUN: %clang -march=graniterapids-d -m64 -E -dM %s -o - 2>&1 \
 // RUN:     --target=x86_64 \
 // RUN:   | FileCheck -match-full-lines %s -check-prefixes=CHECK_GNR_M64,CHECK_GNRD_M64
+// RUN: %clang -march=diamondrapids -m64 -E -dM %s -o - 2>&1 \
+// RUN:     --target=x86_64 \
+// RUN:   | FileCheck -match-full-lines %s -check-prefixes=CHECK_GNR_M64,CHECK_GNRD_M64,CHECK_DMR_M64
 // CHECK_GNR_M64: #define __AES__ 1
+// CHECK_DMR_M64: #define __AMX_AVX512__ 1
 // CHECK_GNR_M64: #define __AMX_BF16__ 1
 // CHECK_GNR_M64-NOT: #define __AMX_COMPLEX__ 1
 // CHECK_GNRD_M64: #define __AMX_COMPLEX__ 1
 // CHECK_GNR_M64: #define __AMX_FP16__ 1
+// CHECK_DMR_M64: #define __AMX_FP8__ 1
 // CHECK_GNR_M64: #define __AMX_INT8__ 1
+// CHECK_DMR_M64: #define __AMX_MOVRS__ 1
+// CHECK_DMR_M64: #define __AMX_TF32__ 1
 // CHECK_GNR_M64: #define __AMX_TILE__ 1
+// CHECK_DMR_M64: #define __AMX_TRANSPOSE__ 1
+// CHECK_DMR_M64: #define __AVX10_2_512__ 1
+// CHECK_DMR_M64: #define __AVX10_2__ 1
 // CHECK_GNR_M64: #define __AVX2__ 1
 // CHECK_GNR_M64: #define __AVX512BF16__ 1
 // CHECK_GNR_M64: #define __AVX512BITALG__ 1
@@ -1969,13 +2006,21 @@
 // CHECK_GNR_M64: #define __AVX512VL__ 1
 // CHECK_GNR_M64: #define __AVX512VNNI__ 1
 // CHECK_GNR_M64: #define __AVX512VPOPCNTDQ__ 1
+// CHECK_DMR_M64: #define __AVXIFMA__ 1
+// CHECK_DMR_M64: #define __AVXNECONVERT__ 1
+// CHECK_DMR_M64: #define __AVXVNNIINT16__ 1
+// CHECK_DMR_M64: #define __AVXVNNIINT8__ 1
 // CHECK_GNR_M64: #define __AVXVNNI__ 1
 // CHECK_GNR_M64: #define __AVX__ 1
 // CHECK_GNR_M64: #define __BMI2__ 1
 // CHECK_GNR_M64: #define __BMI__ 1
+// CHECK_DMR_M64: #define __CCMP__ 1
+// CHECK_DMR_M64: #define __CF__ 1
 // CHECK_GNR_M64: #define __CLDEMOTE__ 1
 // CHECK_GNR_M64: #define __CLFLUSHOPT__ 1
 // CHECK_GNR_M64: #define __CLWB__ 1
+// CHECK_DMR_M64: #define __CMPCCXADD__ 1
+// CHECK_DMR_M64: #define __EGPR__ 1
 // CHECK_GNR_M64: #define __ENQCMD__ 1
 // CHECK_GNR_M64: #define __EVEX256__ 1
 // CHECK_GNR_M64: #define __EVEX512__ 1
@@ -1986,20 +2031,28 @@
 // CHECK_GNR_M64: #define __LZCNT__ 1
 // CHECK_GNR_M64: #define __MMX__ 1
 // CHECK_GNR_M64: #define __MOVBE__ 1
+// CHECK_DMR_M64: #define __MOVRS__ 1
+// CHECK_DMR_M64: #define __NDD__ 1
+// CHECK_DMR_M64: #define __NF__ 1
 // CHECK_GNR_M64: #define __PCLMUL__ 1
 // CHECK_GNR_M64: #define __PCONFIG__ 1
 // CHECK_GNR_M64: #define __PKU__ 1
 // CHECK_GNR_M64: #define __POPCNT__ 1
+// CHECK_DMR_M64: #define __PPX__ 1
 // CHECK_GNR_M64: #define __PREFETCHI__ 1
 // CHECK_GNR_M64: #define __PRFCHW__ 1
 // CHECK_GNR_M64: #define __PTWRITE__ 1
+// CHECK_DMR_M64: #define __PUSH2POP2__ 1
 // CHECK_GNR_M64: #define __RDPID__ 1
 // CHECK_GNR_M64: #define __RDRND__ 1
 // CHECK_GNR_M64: #define __RDSEED__ 1
 // CHECK_GNR_M64: #define __SERIALIZE__ 1
 // CHECK_GNR_M64: #define __SGX__ 1
+// CHECK_DMR_M64: #define __SHA512__ 1
 // CHECK_GNR_M64: #define __SHA__ 1
 // CHECK_GNR_M64: #define __SHSTK__ 1
+// CHECK_DMR_M64: #define __SM3__ 1
+// CHECK_DMR_M64: #define __SM4__ 1
 // CHECK_GNR_M64: #define __SSE2__ 1
 // CHECK_GNR_M64: #define __SSE3__ 1
 // CHECK_GNR_M64: #define __SSE4_1__ 1
@@ -2016,6 +2069,7 @@
 // CHECK_GNR_M64: #define __XSAVEOPT__ 1
 // CHECK_GNR_M64: #define __XSAVES__ 1
 // CHECK_GNR_M64: #define __XSAVE__ 1
+// CHECK_DMR_M64: #define __ZU__ 1
 // CHECK_GNR_M64: #define __amd64 1
 // CHECK_GNR_M64: #define __amd64__ 1
 // CHECK_GNR_M64: #define __corei7 1
diff --git a/compiler-rt/lib/builtins/cpu_model/x86.c b/compiler-rt/lib/builtins/cpu_model/x86.c
index bfa478c4427a5b..3315dceb7f5622 100644
--- a/compiler-rt/lib/builtins/cpu_model/x86.c
+++ b/compiler-rt/lib/builtins/cpu_model/x86.c
@@ -103,6 +103,7 @@ enum ProcessorSubtypes {
   INTEL_COREI7_ARROWLAKE_S,
   INTEL_COREI7_PANTHERLAKE,
   AMDFAM1AH_ZNVER5,
+  INTEL_COREI7_DIAMONDRAPIDS,
   CPU_SUBTYPE_MAX
 };
 
@@ -600,6 +601,19 @@ static const char *getIntelProcessorTypeAndSubtype(unsigned Family,
       break;
     }
     break;
+  case 19:
+    switch (Model) {
+    // Diamond Rapids:
+    case 0x01:
+      CPU = "diamondrapids";
+      *Type = INTEL_COREI7;
+      *Subtype = INTEL_COREI7_DIAMONDRAPIDS;
+      break;
+
+    default: // Unknown family 19 CPU.
+      break;
+    }
+    break;
   default:
     break; // Unknown.
   }
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 0c1019c2fdca03..03c758c4e7f4b6 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -237,6 +237,8 @@ Changes to the X86 Backend
 
 * Supported ISA of `MSR_IMM`.
 
+* Supported ``-mcpu=diamondrapids``
+
 Changes to the OCaml bindings
 -----------------------------
 
diff --git a/llvm/include/llvm/TargetParser/X86TargetParser.def b/llvm/include/llvm/TargetParser/X86TargetParser.def
index 5cad8e117f4ee2..5b719a2b0eb399 100644
--- a/llvm/include/llvm/TargetParser/X86TargetParser.def
+++ b/llvm/include/llvm/TargetParser/X86TargetParser.def
@@ -107,6 +107,7 @@ X86_CPU_SUBTYPE(INTEL_COREI7_ARROWLAKE,      "arrowlake")
 X86_CPU_SUBTYPE(INTEL_COREI7_ARROWLAKE_S,    "arrowlake-s")
 X86_CPU_SUBTYPE(INTEL_COREI7_PANTHERLAKE,    "pantherlake")
 X86_CPU_SUBTYPE(AMDFAM1AH_ZNVER5,            "znver5")
+X86_CPU_SUBTYPE(INTEL_COREI7_DIAMONDRAPIDS,  "diamondrapids")
 
 // Alternate names supported by __builtin_cpu_is and target multiversioning.
 X86_CPU_SUBTYPE_ALIAS(INTEL_COREI7_ALDERLAKE, "raptorlake")
diff --git a/llvm/include/llvm/TargetParser/X86TargetParser.h b/llvm/include/llvm/TargetParser/X86TargetParser.h
index 0e17c4674719cf..8447aca7bb92ae 100644
--- a/llvm/include/llvm/TargetParser/X86TargetParser.h
+++ b/llvm/include/llvm/TargetParser/X86TargetParser.h
@@ -121,6 +121,7 @@ enum CPUKind {
   CK_GraniterapidsD,
   CK_Emeraldrapids,
   CK_Clearwaterforest,
+  CK_Diamondrapids,
   CK_KNL,
   CK_KNM,
   CK_Lakemont,
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index 75224d5b26e33f..5722167beca9f8 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -1155,6 +1155,33 @@ def ProcessorFeatures {
   list<SubtargetFeature> GNRDFeatures =
     !listconcat(GNRFeatures, GNRDAdditionalFeatures);
 
+  // Diamond Rapids
+  list<SubtargetFeature> DMRAdditionalFeatures = [FeatureAVX10_2_512,
+                                                  FeatureSM4,
+                                                  FeatureCMPCCXADD,
+                                                  FeatureAVXIFMA,
+                                                  FeatureAVXNECONVERT,
+                                                  FeatureAVXVNNIINT8,
+                                                  FeatureAVXVNNIINT16,
+                                                  FeatureSHA512,
+                                                  FeatureSM3,
+                                                  FeatureEGPR,
+                                                  FeatureZU,
+                                                  FeatureCCMP,
+                                                  FeaturePush2Pop2,
+                                                  FeaturePPX,
+                                                  FeatureNDD,
+                                                  FeatureNF,
+                                                  FeatureCF,
+                                                  FeatureMOVRS,
+                                                  FeatureAMXMOVRS,
+                                                  FeatureAMXAVX512,
+                                                  FeatureAMXFP8,
+                                                  FeatureAMXTF32,
+                                                  FeatureAMXTRANSPOSE];
+  list<SubtargetFeature> DMRFeatures =
+    !listconcat(GNRDFeatures, DMRAdditionalFeatures);
+
   // Atom
   list<SubtargetFeature> AtomFeatures = [FeatureX87,
                                          FeatureCX8,
@@ -1856,6 +1883,8 @@ foreach P = ["graniterapids-d", "graniterapids_d"] in {
 def : ProcModel<P, SapphireRapidsModel,
                 ProcessorFeatures.GNRDFeatures, ProcessorFeatures.GNRTuning>;
 }
+def : ProcModel<"diamondrapids", SapphireRapidsModel,
+                ProcessorFeatures.DMRFeatures, ProcessorFeatures.GNRTuning>;
 
 // AMD CPUs.
 
diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp
index a7891d799ae409..b295db5a29c368 100644
--- a/llvm/lib/TargetParser/Host.cpp
+++ b/llvm/lib/TargetParser/Host.cpp
@@ -1010,6 +1010,19 @@ static StringRef getIntelProcessorTypeAndSubtype(unsigned Family,
     CPU = "pentium4";
     break;
   }
+  case 19:
+    switch (Model) {
+    // Diamond Rapids:
+    case 0x01:
+      CPU = "diamondrapids";
+      *Type = X86::INTEL_COREI7;
+      *Subtype = X86::INTEL_COREI7_DIAMONDRAPIDS;
+      break;
+
+    default: // Unknown family 19 CPU.
+      break;
+    }
+    break;
   default:
     break; // Unknown.
   }
diff --git a/llvm/lib/TargetParser/X86TargetParser.cpp b/llvm/lib/TargetParser/X86TargetParser.cpp
index 0da740743c9b7c..cc356186188913 100644
--- a/llvm/lib/TargetParser/X86TargetParser.cpp
+++ b/llvm/lib/TargetParser/X86TargetParser.cpp
@@ -138,6 +138,14 @@ constexpr FeatureBitset FeaturesSapphireRapids =
     FeatureWAITPKG;
 constexpr FeatureBitset FeaturesGraniteRapids =
     FeaturesSapphireRapids | FeatureAMX_FP16 | FeaturePREFETCHI;
+constexpr FeatureBitset FeaturesDiamondRapids =
+    FeaturesGraniteRapids | FeatureAMX_COMPLEX | FeatureAVX10_2_512 |
+    FeatureCMPCCXADD | FeatureAVXIFMA | FeatureAVXNECONVERT |
+    FeatureAVXVNNIINT8 | FeatureAVXVNNIINT16 | FeatureSHA512 | FeatureSM3 |
+    FeatureSM4 | FeatureEGPR | FeatureZU | FeatureCCMP | FeaturePush2Pop2 |
+    FeaturePPX | FeatureNDD | FeatureNF | FeatureCF | FeatureMOVRS |
+    FeatureAMX_MOVRS | FeatureAMX_AVX512 | FeatureAMX_FP8 | FeatureAMX_TF32 |
+    FeatureAMX_TRANSPOSE;
 
 // Intel Atom processors.
 // Bonnell has feature parity with Core2 and adds MOVBE.
@@ -381,6 +389,8 @@ constexpr ProcInfo Processors[] = {
   { {"emeraldrapids"}, CK_Emeraldrapids, FEATURE_AVX512FP16, FeaturesSapphireRapids, 'n', false },
   // Clearwaterforest microarchitecture based processors.
   { {"clearwaterforest"}, CK_Lunarlake, FEATURE_AVX2, FeaturesClearwaterforest, 'p', false },
+  // Diamond Rapids microarchitecture based processors.
+  { {"diamondrapids"}, CK_Diamondrapids, FEATURE_AVX10_2_512, FeaturesDiamondRapids, 'z', false },
   // Knights Landing processor.
   { {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL, 'Z', false },
   { {"mic_avx512"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL, 'Z', true },
diff --git a/llvm/test/CodeGen/X86/cpus-intel.ll b/llvm/test/CodeGen/X86/cpus-intel.ll
index 5e4d09e081fec9..40c38c2e828498 100644
--- a/llvm/test/CodeGen/X86/cpus-intel.ll
+++ b/llvm/test/CodeGen/X86/cpus-intel.ll
@@ -39,6 +39,7 @@
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=gracemont 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pantherlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=clearwaterforest 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=diamondrapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=nocona 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=core2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
@@ -104,6 +105,7 @@
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=gracemont 2>&1 | FileCheck %s --...
[truncated]

llvmbot · 2024-11-18T01:10:38Z

@llvm/pr-subscribers-clang

Author: Freddy Ye (FreddyLeaf)

Changes

Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368

Patch is 20.50 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/116564.diff

16 Files Affected:

(modified) clang/docs/ReleaseNotes.rst (+2)
(modified) clang/lib/Basic/Targets/X86.cpp (+2)
(modified) clang/test/CodeGen/attr-cpuspecific-cpus.c (+1)
(modified) clang/test/CodeGen/attr-target-mv.c (+1)
(modified) clang/test/CodeGen/target-builtin-noerror.c (+1)
(modified) clang/test/Driver/x86-march.c (+4)
(modified) clang/test/Misc/target-invalid-cpu-note/x86.c (+4)
(modified) clang/test/Preprocessor/predefined-arch-macros.c (+54)
(modified) compiler-rt/lib/builtins/cpu_model/x86.c (+14)
(modified) llvm/docs/ReleaseNotes.md (+2)
(modified) llvm/include/llvm/TargetParser/X86TargetParser.def (+1)
(modified) llvm/include/llvm/TargetParser/X86TargetParser.h (+1)
(modified) llvm/lib/Target/X86/X86.td (+29)
(modified) llvm/lib/TargetParser/Host.cpp (+13)
(modified) llvm/lib/TargetParser/X86TargetParser.cpp (+10)
(modified) llvm/test/CodeGen/X86/cpus-intel.ll (+2)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index a8830a5658c7da..044f62e770a7a0 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -769,6 +769,8 @@ X86 Support
 - Support ISA of ``AMX-TF32``.
 - Support ISA of ``MOVRS``.
 
+- Supported ``-march/tune=diamondrapids``
+
 Arm and AArch64 Support
 ^^^^^^^^^^^^^^^^^^^^^^^
 
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index 086b4415412e67..5993257e27d5a9 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -667,6 +667,7 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
   case CK_GraniterapidsD:
   case CK_Emeraldrapids:
   case CK_Clearwaterforest:
+  case CK_Diamondrapids:
     // FIXME: Historically, we defined this legacy name, it would be nice to
     // remove it at some point. We've never exposed fine-grained names for
     // recent primary x86 CPUs, and we should keep it that way.
@@ -1651,6 +1652,7 @@ std::optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const {
     case CK_GraniterapidsD:
     case CK_Emeraldrapids:
     case CK_Clearwaterforest:
+    case CK_Diamondrapids:
     case CK_KNL:
     case CK_KNM:
     // K7
diff --git a/clang/test/CodeGen/attr-cpuspecific-cpus.c b/clang/test/CodeGen/attr-cpuspecific-cpus.c
index dd154fd227b25b..1dd095ec9e191f 100644
--- a/clang/test/CodeGen/attr-cpuspecific-cpus.c
+++ b/clang/test/CodeGen/attr-cpuspecific-cpus.c
@@ -43,6 +43,7 @@ ATTR(cpu_specific(icelake_client)) void CPU(void){}
 ATTR(cpu_specific(tigerlake)) void CPU(void){}
 ATTR(cpu_specific(alderlake)) void CPU(void){}
 ATTR(cpu_specific(sapphirerapids)) void CPU(void){}
+ATTR(cpu_specific(diamondrapids)) void CPU(void){}
 
 // ALIAS CPUs
 ATTR(cpu_specific(pentium_iii_no_xmm_regs)) void CPU0(void){}
diff --git a/clang/test/CodeGen/attr-target-mv.c b/clang/test/CodeGen/attr-target-mv.c
index 2c4b95ca04370a..6911b55203b7e7 100644
--- a/clang/test/CodeGen/attr-target-mv.c
+++ b/clang/test/CodeGen/attr-target-mv.c
@@ -29,6 +29,7 @@ int __attribute__((target("arch=lunarlake"))) foo(void) {return 23;}
 int __attribute__((target("arch=gracemont"))) foo(void) {return 24;}
 int __attribute__((target("arch=pantherlake"))) foo(void) {return 25;}
 int __attribute__((target("arch=clearwaterforest"))) foo(void) {return 26;}
+int __attribute__((target("arch=diamondrapids"))) foo(void) {return 27;}
 int __attribute__((target("default"))) foo(void) { return 2; }
 
 int bar(void) {
diff --git a/clang/test/CodeGen/target-builtin-noerror.c b/clang/test/CodeGen/target-builtin-noerror.c
index 1e53621bc6b5ae..0bbd8c3e5ddd81 100644
--- a/clang/test/CodeGen/target-builtin-noerror.c
+++ b/clang/test/CodeGen/target-builtin-noerror.c
@@ -209,4 +209,5 @@ void verifycpustrings(void) {
   (void)__builtin_cpu_is("znver3");
   (void)__builtin_cpu_is("znver4");
   (void)__builtin_cpu_is("znver5");
+  (void)__builtin_cpu_is("diamondrapids");
 }
diff --git a/clang/test/Driver/x86-march.c b/clang/test/Driver/x86-march.c
index 3bc2a82ae778d6..341f01c8d668df 100644
--- a/clang/test/Driver/x86-march.c
+++ b/clang/test/Driver/x86-march.c
@@ -120,6 +120,10 @@
 // RUN:   | FileCheck %s -check-prefix=clearwaterforest
 // clearwaterforest: "-target-cpu" "clearwaterforest"
 //
+// RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=diamondrapids 2>&1 \
+// RUN:   | FileCheck %s -check-prefix=diamondrapids
+// diamondrapids: "-target-cpu" "diamondrapids"
+//
 // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=lakemont 2>&1 \
 // RUN:   | FileCheck %s -check-prefix=lakemont
 // lakemont: "-target-cpu" "lakemont"
diff --git a/clang/test/Misc/target-invalid-cpu-note/x86.c b/clang/test/Misc/target-invalid-cpu-note/x86.c
index 7879676040af46..f89cdc2aa573ff 100644
--- a/clang/test/Misc/target-invalid-cpu-note/x86.c
+++ b/clang/test/Misc/target-invalid-cpu-note/x86.c
@@ -69,6 +69,7 @@
 // X86-SAME: {{^}}, graniterapids-d
 // X86-SAME: {{^}}, emeraldrapids
 // X86-SAME: {{^}}, clearwaterforest
+// X86-SAME: {{^}}, diamondrapids
 // X86-SAME: {{^}}, knl
 // X86-SAME: {{^}}, knm
 // X86-SAME: {{^}}, lakemont
@@ -155,6 +156,7 @@
 // X86_64-SAME: {{^}}, graniterapids-d
 // X86_64-SAME: {{^}}, emeraldrapids
 // X86_64-SAME: {{^}}, clearwaterforest
+// X86_64-SAME: {{^}}, diamondrapids
 // X86_64-SAME: {{^}}, knl
 // X86_64-SAME: {{^}}, knm
 // X86_64-SAME: {{^}}, k8
@@ -250,6 +252,7 @@
 // TUNE_X86-SAME: {{^}}, graniterapids-d
 // TUNE_X86-SAME: {{^}}, emeraldrapids
 // TUNE_X86-SAME: {{^}}, clearwaterforest
+// TUNE_X86-SAME: {{^}}, diamondrapids
 // TUNE_X86-SAME: {{^}}, knl
 // TUNE_X86-SAME: {{^}}, knm
 // TUNE_X86-SAME: {{^}}, lakemont
@@ -352,6 +355,7 @@
 // TUNE_X86_64-SAME: {{^}}, graniterapids-d
 // TUNE_X86_64-SAME: {{^}}, emeraldrapids
 // TUNE_X86_64-SAME: {{^}}, clearwaterforest
+// TUNE_X86_64-SAME: {{^}}, diamondrapids
 // TUNE_X86_64-SAME: {{^}}, knl
 // TUNE_X86_64-SAME: {{^}}, knm
 // TUNE_X86_64-SAME: {{^}}, lakemont
diff --git a/clang/test/Preprocessor/predefined-arch-macros.c b/clang/test/Preprocessor/predefined-arch-macros.c
index 35801e758cc58a..20aa2d4e0a54cb 100644
--- a/clang/test/Preprocessor/predefined-arch-macros.c
+++ b/clang/test/Preprocessor/predefined-arch-macros.c
@@ -1867,13 +1867,23 @@
 // RUN: %clang -march=graniterapids-d -m32 -E -dM %s -o - 2>&1 \
 // RUN:     --target=i386 \
 // RUN:   | FileCheck -match-full-lines %s -check-prefixes=CHECK_GNR_M32,CHECK_GNRD_M32
+// RUN: %clang -march=diamondrapids -m32 -E -dM %s -o - 2>&1 \
+// RUN:     --target=i386 \
+// RUN:   | FileCheck -match-full-lines %s -check-prefixes=CHECK_GNR_M32,CHECK_GNRD_M32,CHECK_DMR_M32
 // CHECK_GNR_M32: #define __AES__ 1
+// CHECK_DMR_M32: #define __AMX_AVX512__ 1
 // CHECK_GNR_M32: #define __AMX_BF16__ 1
 // CHECK_GNR_M32-NOT: #define __AMX_COMPLEX__ 1
 // CHECK_GNRD_M32: #define __AMX_COMPLEX__ 1
 // CHECK_GNR_M32: #define __AMX_FP16__ 1
+// CHECK_DMR_M32: #define __AMX_FP8__ 1
 // CHECK_GNR_M32: #define __AMX_INT8__ 1
+// CHECK_DMR_M32: #define __AMX_MOVRS__ 1
+// CHECK_DMR_M32: #define __AMX_TF32__ 1
 // CHECK_GNR_M32: #define __AMX_TILE__ 1
+// CHECK_DMR_M32: #define __AMX_TRANSPOSE__ 1
+// CHECK_DMR_M32: #define __AVX10_2_512__ 1
+// CHECK_DMR_M32: #define __AVX10_2__ 1
 // CHECK_GNR_M32: #define __AVX2__ 1
 // CHECK_GNR_M32: #define __AVX512BF16__ 1
 // CHECK_GNR_M32: #define __AVX512BITALG__ 1
@@ -1888,13 +1898,21 @@
 // CHECK_GNR_M32: #define __AVX512VL__ 1
 // CHECK_GNR_M32: #define __AVX512VNNI__ 1
 // CHECK_GNR_M32: #define __AVX512VPOPCNTDQ__ 1
+// CHECK_DMR_M32: #define __AVXIFMA__ 1
+// CHECK_DMR_M32: #define __AVXNECONVERT__ 1
+// CHECK_DMR_M32: #define __AVXVNNIINT16__ 1
+// CHECK_DMR_M32: #define __AVXVNNIINT8__ 1
 // CHECK_GNR_M32: #define __AVXVNNI__ 1
 // CHECK_GNR_M32: #define __AVX__ 1
 // CHECK_GNR_M32: #define __BMI2__ 1
 // CHECK_GNR_M32: #define __BMI__ 1
+// CHECK_DMR_M32: #define __CCMP__ 1
+// CHECK_DMR_M32: #define __CF__ 1
 // CHECK_GNR_M32: #define __CLDEMOTE__ 1
 // CHECK_GNR_M32: #define __CLFLUSHOPT__ 1
 // CHECK_GNR_M32: #define __CLWB__ 1
+// CHECK_DMR_M32: #define __CMPCCXADD__ 1
+// CHECK_DMR_M32: #define __EGPR__ 1
 // CHECK_GNR_M32: #define __ENQCMD__ 1
 // CHECK_GNR_M32: #define __EVEX256__ 1
 // CHECK_GNR_M32: #define __EVEX512__ 1
@@ -1905,20 +1923,28 @@
 // CHECK_GNR_M32: #define __LZCNT__ 1
 // CHECK_GNR_M32: #define __MMX__ 1
 // CHECK_GNR_M32: #define __MOVBE__ 1
+// CHECK_DMR_M32: #define __MOVRS__ 1
+// CHECK_DMR_M32: #define __NDD__ 1
+// CHECK_DMR_M32: #define __NF__ 1
 // CHECK_GNR_M32: #define __PCLMUL__ 1
 // CHECK_GNR_M32: #define __PCONFIG__ 1
 // CHECK_GNR_M32: #define __PKU__ 1
 // CHECK_GNR_M32: #define __POPCNT__ 1
+// CHECK_DMR_M32: #define __PPX__ 1
 // CHECK_GNR_M32: #define __PREFETCHI__ 1
 // CHECK_GNR_M32: #define __PRFCHW__ 1
 // CHECK_GNR_M32: #define __PTWRITE__ 1
+// CHECK_DMR_M32: #define __PUSH2POP2__ 1
 // CHECK_GNR_M32: #define __RDPID__ 1
 // CHECK_GNR_M32: #define __RDRND__ 1
 // CHECK_GNR_M32: #define __RDSEED__ 1
 // CHECK_GNR_M32: #define __SERIALIZE__ 1
 // CHECK_GNR_M32: #define __SGX__ 1
+// CHECK_DMR_M32: #define __SHA512__ 1
 // CHECK_GNR_M32: #define __SHA__ 1
 // CHECK_GNR_M32: #define __SHSTK__ 1
+// CHECK_DMR_M32: #define __SM3__ 1
+// CHECK_DMR_M32: #define __SM4__ 1
 // CHECK_GNR_M32: #define __SSE2__ 1
 // CHECK_GNR_M32: #define __SSE3__ 1
 // CHECK_GNR_M32: #define __SSE4_1__ 1
@@ -1935,6 +1961,7 @@
 // CHECK_GNR_M32: #define __XSAVEOPT__ 1
 // CHECK_GNR_M32: #define __XSAVES__ 1
 // CHECK_GNR_M32: #define __XSAVE__ 1
+// CHECK_DMR_M32: #define __ZU__ 1
 // CHECK_GNR_M32: #define __corei7 1
 // CHECK_GNR_M32: #define __corei7__ 1
 // CHECK_GNR_M32: #define __i386 1
@@ -1948,13 +1975,23 @@
 // RUN: %clang -march=graniterapids-d -m64 -E -dM %s -o - 2>&1 \
 // RUN:     --target=x86_64 \
 // RUN:   | FileCheck -match-full-lines %s -check-prefixes=CHECK_GNR_M64,CHECK_GNRD_M64
+// RUN: %clang -march=diamondrapids -m64 -E -dM %s -o - 2>&1 \
+// RUN:     --target=x86_64 \
+// RUN:   | FileCheck -match-full-lines %s -check-prefixes=CHECK_GNR_M64,CHECK_GNRD_M64,CHECK_DMR_M64
 // CHECK_GNR_M64: #define __AES__ 1
+// CHECK_DMR_M64: #define __AMX_AVX512__ 1
 // CHECK_GNR_M64: #define __AMX_BF16__ 1
 // CHECK_GNR_M64-NOT: #define __AMX_COMPLEX__ 1
 // CHECK_GNRD_M64: #define __AMX_COMPLEX__ 1
 // CHECK_GNR_M64: #define __AMX_FP16__ 1
+// CHECK_DMR_M64: #define __AMX_FP8__ 1
 // CHECK_GNR_M64: #define __AMX_INT8__ 1
+// CHECK_DMR_M64: #define __AMX_MOVRS__ 1
+// CHECK_DMR_M64: #define __AMX_TF32__ 1
 // CHECK_GNR_M64: #define __AMX_TILE__ 1
+// CHECK_DMR_M64: #define __AMX_TRANSPOSE__ 1
+// CHECK_DMR_M64: #define __AVX10_2_512__ 1
+// CHECK_DMR_M64: #define __AVX10_2__ 1
 // CHECK_GNR_M64: #define __AVX2__ 1
 // CHECK_GNR_M64: #define __AVX512BF16__ 1
 // CHECK_GNR_M64: #define __AVX512BITALG__ 1
@@ -1969,13 +2006,21 @@
 // CHECK_GNR_M64: #define __AVX512VL__ 1
 // CHECK_GNR_M64: #define __AVX512VNNI__ 1
 // CHECK_GNR_M64: #define __AVX512VPOPCNTDQ__ 1
+// CHECK_DMR_M64: #define __AVXIFMA__ 1
+// CHECK_DMR_M64: #define __AVXNECONVERT__ 1
+// CHECK_DMR_M64: #define __AVXVNNIINT16__ 1
+// CHECK_DMR_M64: #define __AVXVNNIINT8__ 1
 // CHECK_GNR_M64: #define __AVXVNNI__ 1
 // CHECK_GNR_M64: #define __AVX__ 1
 // CHECK_GNR_M64: #define __BMI2__ 1
 // CHECK_GNR_M64: #define __BMI__ 1
+// CHECK_DMR_M64: #define __CCMP__ 1
+// CHECK_DMR_M64: #define __CF__ 1
 // CHECK_GNR_M64: #define __CLDEMOTE__ 1
 // CHECK_GNR_M64: #define __CLFLUSHOPT__ 1
 // CHECK_GNR_M64: #define __CLWB__ 1
+// CHECK_DMR_M64: #define __CMPCCXADD__ 1
+// CHECK_DMR_M64: #define __EGPR__ 1
 // CHECK_GNR_M64: #define __ENQCMD__ 1
 // CHECK_GNR_M64: #define __EVEX256__ 1
 // CHECK_GNR_M64: #define __EVEX512__ 1
@@ -1986,20 +2031,28 @@
 // CHECK_GNR_M64: #define __LZCNT__ 1
 // CHECK_GNR_M64: #define __MMX__ 1
 // CHECK_GNR_M64: #define __MOVBE__ 1
+// CHECK_DMR_M64: #define __MOVRS__ 1
+// CHECK_DMR_M64: #define __NDD__ 1
+// CHECK_DMR_M64: #define __NF__ 1
 // CHECK_GNR_M64: #define __PCLMUL__ 1
 // CHECK_GNR_M64: #define __PCONFIG__ 1
 // CHECK_GNR_M64: #define __PKU__ 1
 // CHECK_GNR_M64: #define __POPCNT__ 1
+// CHECK_DMR_M64: #define __PPX__ 1
 // CHECK_GNR_M64: #define __PREFETCHI__ 1
 // CHECK_GNR_M64: #define __PRFCHW__ 1
 // CHECK_GNR_M64: #define __PTWRITE__ 1
+// CHECK_DMR_M64: #define __PUSH2POP2__ 1
 // CHECK_GNR_M64: #define __RDPID__ 1
 // CHECK_GNR_M64: #define __RDRND__ 1
 // CHECK_GNR_M64: #define __RDSEED__ 1
 // CHECK_GNR_M64: #define __SERIALIZE__ 1
 // CHECK_GNR_M64: #define __SGX__ 1
+// CHECK_DMR_M64: #define __SHA512__ 1
 // CHECK_GNR_M64: #define __SHA__ 1
 // CHECK_GNR_M64: #define __SHSTK__ 1
+// CHECK_DMR_M64: #define __SM3__ 1
+// CHECK_DMR_M64: #define __SM4__ 1
 // CHECK_GNR_M64: #define __SSE2__ 1
 // CHECK_GNR_M64: #define __SSE3__ 1
 // CHECK_GNR_M64: #define __SSE4_1__ 1
@@ -2016,6 +2069,7 @@
 // CHECK_GNR_M64: #define __XSAVEOPT__ 1
 // CHECK_GNR_M64: #define __XSAVES__ 1
 // CHECK_GNR_M64: #define __XSAVE__ 1
+// CHECK_DMR_M64: #define __ZU__ 1
 // CHECK_GNR_M64: #define __amd64 1
 // CHECK_GNR_M64: #define __amd64__ 1
 // CHECK_GNR_M64: #define __corei7 1
diff --git a/compiler-rt/lib/builtins/cpu_model/x86.c b/compiler-rt/lib/builtins/cpu_model/x86.c
index bfa478c4427a5b..3315dceb7f5622 100644
--- a/compiler-rt/lib/builtins/cpu_model/x86.c
+++ b/compiler-rt/lib/builtins/cpu_model/x86.c
@@ -103,6 +103,7 @@ enum ProcessorSubtypes {
   INTEL_COREI7_ARROWLAKE_S,
   INTEL_COREI7_PANTHERLAKE,
   AMDFAM1AH_ZNVER5,
+  INTEL_COREI7_DIAMONDRAPIDS,
   CPU_SUBTYPE_MAX
 };
 
@@ -600,6 +601,19 @@ static const char *getIntelProcessorTypeAndSubtype(unsigned Family,
       break;
     }
     break;
+  case 19:
+    switch (Model) {
+    // Diamond Rapids:
+    case 0x01:
+      CPU = "diamondrapids";
+      *Type = INTEL_COREI7;
+      *Subtype = INTEL_COREI7_DIAMONDRAPIDS;
+      break;
+
+    default: // Unknown family 19 CPU.
+      break;
+    }
+    break;
   default:
     break; // Unknown.
   }
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 0c1019c2fdca03..03c758c4e7f4b6 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -237,6 +237,8 @@ Changes to the X86 Backend
 
 * Supported ISA of `MSR_IMM`.
 
+* Supported ``-mcpu=diamondrapids``
+
 Changes to the OCaml bindings
 -----------------------------
 
diff --git a/llvm/include/llvm/TargetParser/X86TargetParser.def b/llvm/include/llvm/TargetParser/X86TargetParser.def
index 5cad8e117f4ee2..5b719a2b0eb399 100644
--- a/llvm/include/llvm/TargetParser/X86TargetParser.def
+++ b/llvm/include/llvm/TargetParser/X86TargetParser.def
@@ -107,6 +107,7 @@ X86_CPU_SUBTYPE(INTEL_COREI7_ARROWLAKE,      "arrowlake")
 X86_CPU_SUBTYPE(INTEL_COREI7_ARROWLAKE_S,    "arrowlake-s")
 X86_CPU_SUBTYPE(INTEL_COREI7_PANTHERLAKE,    "pantherlake")
 X86_CPU_SUBTYPE(AMDFAM1AH_ZNVER5,            "znver5")
+X86_CPU_SUBTYPE(INTEL_COREI7_DIAMONDRAPIDS,  "diamondrapids")
 
 // Alternate names supported by __builtin_cpu_is and target multiversioning.
 X86_CPU_SUBTYPE_ALIAS(INTEL_COREI7_ALDERLAKE, "raptorlake")
diff --git a/llvm/include/llvm/TargetParser/X86TargetParser.h b/llvm/include/llvm/TargetParser/X86TargetParser.h
index 0e17c4674719cf..8447aca7bb92ae 100644
--- a/llvm/include/llvm/TargetParser/X86TargetParser.h
+++ b/llvm/include/llvm/TargetParser/X86TargetParser.h
@@ -121,6 +121,7 @@ enum CPUKind {
   CK_GraniterapidsD,
   CK_Emeraldrapids,
   CK_Clearwaterforest,
+  CK_Diamondrapids,
   CK_KNL,
   CK_KNM,
   CK_Lakemont,
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index 75224d5b26e33f..5722167beca9f8 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -1155,6 +1155,33 @@ def ProcessorFeatures {
   list<SubtargetFeature> GNRDFeatures =
     !listconcat(GNRFeatures, GNRDAdditionalFeatures);
 
+  // Diamond Rapids
+  list<SubtargetFeature> DMRAdditionalFeatures = [FeatureAVX10_2_512,
+                                                  FeatureSM4,
+                                                  FeatureCMPCCXADD,
+                                                  FeatureAVXIFMA,
+                                                  FeatureAVXNECONVERT,
+                                                  FeatureAVXVNNIINT8,
+                                                  FeatureAVXVNNIINT16,
+                                                  FeatureSHA512,
+                                                  FeatureSM3,
+                                                  FeatureEGPR,
+                                                  FeatureZU,
+                                                  FeatureCCMP,
+                                                  FeaturePush2Pop2,
+                                                  FeaturePPX,
+                                                  FeatureNDD,
+                                                  FeatureNF,
+                                                  FeatureCF,
+                                                  FeatureMOVRS,
+                                                  FeatureAMXMOVRS,
+                                                  FeatureAMXAVX512,
+                                                  FeatureAMXFP8,
+                                                  FeatureAMXTF32,
+                                                  FeatureAMXTRANSPOSE];
+  list<SubtargetFeature> DMRFeatures =
+    !listconcat(GNRDFeatures, DMRAdditionalFeatures);
+
   // Atom
   list<SubtargetFeature> AtomFeatures = [FeatureX87,
                                          FeatureCX8,
@@ -1856,6 +1883,8 @@ foreach P = ["graniterapids-d", "graniterapids_d"] in {
 def : ProcModel<P, SapphireRapidsModel,
                 ProcessorFeatures.GNRDFeatures, ProcessorFeatures.GNRTuning>;
 }
+def : ProcModel<"diamondrapids", SapphireRapidsModel,
+                ProcessorFeatures.DMRFeatures, ProcessorFeatures.GNRTuning>;
 
 // AMD CPUs.
 
diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp
index a7891d799ae409..b295db5a29c368 100644
--- a/llvm/lib/TargetParser/Host.cpp
+++ b/llvm/lib/TargetParser/Host.cpp
@@ -1010,6 +1010,19 @@ static StringRef getIntelProcessorTypeAndSubtype(unsigned Family,
     CPU = "pentium4";
     break;
   }
+  case 19:
+    switch (Model) {
+    // Diamond Rapids:
+    case 0x01:
+      CPU = "diamondrapids";
+      *Type = X86::INTEL_COREI7;
+      *Subtype = X86::INTEL_COREI7_DIAMONDRAPIDS;
+      break;
+
+    default: // Unknown family 19 CPU.
+      break;
+    }
+    break;
   default:
     break; // Unknown.
   }
diff --git a/llvm/lib/TargetParser/X86TargetParser.cpp b/llvm/lib/TargetParser/X86TargetParser.cpp
index 0da740743c9b7c..cc356186188913 100644
--- a/llvm/lib/TargetParser/X86TargetParser.cpp
+++ b/llvm/lib/TargetParser/X86TargetParser.cpp
@@ -138,6 +138,14 @@ constexpr FeatureBitset FeaturesSapphireRapids =
     FeatureWAITPKG;
 constexpr FeatureBitset FeaturesGraniteRapids =
     FeaturesSapphireRapids | FeatureAMX_FP16 | FeaturePREFETCHI;
+constexpr FeatureBitset FeaturesDiamondRapids =
+    FeaturesGraniteRapids | FeatureAMX_COMPLEX | FeatureAVX10_2_512 |
+    FeatureCMPCCXADD | FeatureAVXIFMA | FeatureAVXNECONVERT |
+    FeatureAVXVNNIINT8 | FeatureAVXVNNIINT16 | FeatureSHA512 | FeatureSM3 |
+    FeatureSM4 | FeatureEGPR | FeatureZU | FeatureCCMP | FeaturePush2Pop2 |
+    FeaturePPX | FeatureNDD | FeatureNF | FeatureCF | FeatureMOVRS |
+    FeatureAMX_MOVRS | FeatureAMX_AVX512 | FeatureAMX_FP8 | FeatureAMX_TF32 |
+    FeatureAMX_TRANSPOSE;
 
 // Intel Atom processors.
 // Bonnell has feature parity with Core2 and adds MOVBE.
@@ -381,6 +389,8 @@ constexpr ProcInfo Processors[] = {
   { {"emeraldrapids"}, CK_Emeraldrapids, FEATURE_AVX512FP16, FeaturesSapphireRapids, 'n', false },
   // Clearwaterforest microarchitecture based processors.
   { {"clearwaterforest"}, CK_Lunarlake, FEATURE_AVX2, FeaturesClearwaterforest, 'p', false },
+  // Diamond Rapids microarchitecture based processors.
+  { {"diamondrapids"}, CK_Diamondrapids, FEATURE_AVX10_2_512, FeaturesDiamondRapids, 'z', false },
   // Knights Landing processor.
   { {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL, 'Z', false },
   { {"mic_avx512"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL, 'Z', true },
diff --git a/llvm/test/CodeGen/X86/cpus-intel.ll b/llvm/test/CodeGen/X86/cpus-intel.ll
index 5e4d09e081fec9..40c38c2e828498 100644
--- a/llvm/test/CodeGen/X86/cpus-intel.ll
+++ b/llvm/test/CodeGen/X86/cpus-intel.ll
@@ -39,6 +39,7 @@
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=gracemont 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pantherlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=clearwaterforest 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=diamondrapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=nocona 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=core2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
@@ -104,6 +105,7 @@
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=gracemont 2>&1 | FileCheck %s --...
[truncated]

Reland "[X86] Support -march=diamondrapids (llvm#113881)"

043c826

Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368

llvmbot added clang Clang issues not falling into any other category compiler-rt backend:X86 clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang:frontend Language frontend issues, e.g. anything involving "Sema" compiler-rt:builtins labels Nov 18, 2024

phoebewang approved these changes Nov 18, 2024

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FreddyLeaf merged commit 97836be into llvm:main Nov 18, 2024
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FreddyLeaf deleted the reland_diamondrapids branch November 18, 2024 02:40

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Reland "[X86] Support -march=diamondrapids (#113881)" #116564

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Reland "[X86] Support -march=diamondrapids (#113881)" #116564

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