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[X86] Add missing reg/imm attributes to VRNDSCALES instruction names #117203

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Merged
merged 1 commit into from
Nov 22, 2024
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[X86] Add missing reg/imm attributes to VRNDSCALES instruction names #117203

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16 changes: 8 additions & 8 deletions llvm/lib/Target/X86/X86CompressEVEX.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -154,14 +154,14 @@ static bool performCustomAdjustments(MachineInstr &MI, unsigned NewOpc) {
case X86::VRNDSCALEPDZ256rmi:
case X86::VRNDSCALEPSZ256rri:
case X86::VRNDSCALEPSZ256rmi:
case X86::VRNDSCALESDZr:
case X86::VRNDSCALESDZm:
case X86::VRNDSCALESSZr:
case X86::VRNDSCALESSZm:
case X86::VRNDSCALESDZr_Int:
case X86::VRNDSCALESDZm_Int:
case X86::VRNDSCALESSZr_Int:
case X86::VRNDSCALESSZm_Int:
case X86::VRNDSCALESDZrri:
case X86::VRNDSCALESDZrmi:
case X86::VRNDSCALESSZrri:
case X86::VRNDSCALESSZrmi:
case X86::VRNDSCALESDZrri_Int:
case X86::VRNDSCALESDZrmi_Int:
case X86::VRNDSCALESSZrri_Int:
case X86::VRNDSCALESSZrmi_Int:
const MachineOperand &Imm = MI.getOperand(MI.getNumExplicitOperands() - 1);
int64_t ImmVal = Imm.getImm();
// Ensure that only bits 3:0 of the immediate are used.
Expand Down
14 changes: 7 additions & 7 deletions llvm/lib/Target/X86/X86InstrAVX512.td
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Original file line number Diff line number Diff line change
Expand Up @@ -9596,22 +9596,22 @@ defm VSQRT : avx512_sqrt_scalar_all<0x51, "vsqrt", SchedWriteFSqrtSizes>, VEX_LI
multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
X86FoldableSchedWrite sched, X86VectorVTInfo _> {
let ExeDomain = _.ExeDomain in {
defm r_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
defm rri_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
(ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
"$src3, $src2, $src1", "$src1, $src2, $src3",
(_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
(i32 timm:$src3)))>,
Sched<[sched]>, SIMD_EXC;

let Uses = [MXCSR] in
defm rb_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
defm rrib_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
(ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
"$src3, {sae}, $src2, $src1", "$src1, $src2, {sae}, $src3",
(_.VT (X86RndScalesSAE (_.VT _.RC:$src1), (_.VT _.RC:$src2),
(i32 timm:$src3)))>, EVEX_B,
Sched<[sched]>;

defm m_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
defm rmi_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
(ins _.RC:$src1, _.IntScalarMemOp:$src2, i32u8imm:$src3),
OpcodeStr,
"$src3, $src2, $src1", "$src1, $src2, $src3",
Expand All @@ -9620,13 +9620,13 @@ multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
Sched<[sched.Folded, sched.ReadAfterFold]>, SIMD_EXC;

let isCodeGenOnly = 1, hasSideEffects = 0, Predicates = [HasAVX512] in {
def r : I<opc, MRMSrcReg, (outs _.FRC:$dst),
def rri : I<opc, MRMSrcReg, (outs _.FRC:$dst),
(ins _.FRC:$src1, _.FRC:$src2, i32u8imm:$src3),
OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
[]>, Sched<[sched]>, SIMD_EXC;

let mayLoad = 1 in
def m : I<opc, MRMSrcMem, (outs _.FRC:$dst),
def rmi : I<opc, MRMSrcMem, (outs _.FRC:$dst),
(ins _.FRC:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
[]>, Sched<[sched.Folded, sched.ReadAfterFold]>, SIMD_EXC;
Expand All @@ -9635,13 +9635,13 @@ multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,

let Predicates = [HasAVX512] in {
def : Pat<(X86any_VRndScale _.FRC:$src1, timm:$src2),
(_.EltVT (!cast<Instruction>(NAME#r) (_.EltVT (IMPLICIT_DEF)),
(_.EltVT (!cast<Instruction>(NAME#rri) (_.EltVT (IMPLICIT_DEF)),
_.FRC:$src1, timm:$src2))>;
}

let Predicates = [HasAVX512, OptForSize] in {
def : Pat<(X86any_VRndScale (_.ScalarLdFrag addr:$src1), timm:$src2),
(_.EltVT (!cast<Instruction>(NAME#m) (_.EltVT (IMPLICIT_DEF)),
(_.EltVT (!cast<Instruction>(NAME#rmi) (_.EltVT (IMPLICIT_DEF)),
addr:$src1, timm:$src2))>;
}
}
Expand Down
42 changes: 21 additions & 21 deletions llvm/lib/Target/X86/X86InstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -6971,16 +6971,16 @@ static bool hasUndefRegUpdate(unsigned Opcode, unsigned OpNum,
case X86::VGETMANTSSZrri:
case X86::VGETMANTSSZrrib:
case X86::VGETMANTSSZrmi:
case X86::VRNDSCALESDZr:
case X86::VRNDSCALESDZr_Int:
case X86::VRNDSCALESDZrb_Int:
case X86::VRNDSCALESDZm:
case X86::VRNDSCALESDZm_Int:
case X86::VRNDSCALESSZr:
case X86::VRNDSCALESSZr_Int:
case X86::VRNDSCALESSZrb_Int:
case X86::VRNDSCALESSZm:
case X86::VRNDSCALESSZm_Int:
case X86::VRNDSCALESDZrri:
case X86::VRNDSCALESDZrri_Int:
case X86::VRNDSCALESDZrrib_Int:
case X86::VRNDSCALESDZrmi:
case X86::VRNDSCALESDZrmi_Int:
case X86::VRNDSCALESSZrri:
case X86::VRNDSCALESSZrri_Int:
case X86::VRNDSCALESSZrrib_Int:
case X86::VRNDSCALESSZrmi:
case X86::VRNDSCALESSZrmi_Int:
case X86::VRCP14SDZrr:
case X86::VRCP14SDZrm:
case X86::VRCP14SSZrr:
Expand All @@ -6998,11 +6998,11 @@ static bool hasUndefRegUpdate(unsigned Opcode, unsigned OpNum,
case X86::VGETMANTSHZrri:
case X86::VGETMANTSHZrrib:
case X86::VGETMANTSHZrmi:
case X86::VRNDSCALESHZr:
case X86::VRNDSCALESHZr_Int:
case X86::VRNDSCALESHZrb_Int:
case X86::VRNDSCALESHZm:
case X86::VRNDSCALESHZm_Int:
case X86::VRNDSCALESHZrri:
case X86::VRNDSCALESHZrri_Int:
case X86::VRNDSCALESHZrrib_Int:
case X86::VRNDSCALESHZrmi:
case X86::VRNDSCALESHZrmi_Int:
case X86::VSQRTSHZr:
case X86::VSQRTSHZr_Int:
case X86::VSQRTSHZrb_Int:
Expand Down Expand Up @@ -7790,9 +7790,9 @@ static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
case X86::VREDUCESSZrri:
case X86::VREDUCESSZrrik:
case X86::VREDUCESSZrrikz:
case X86::VRNDSCALESSZr_Int:
case X86::VRNDSCALESSZr_Intk:
case X86::VRNDSCALESSZr_Intkz:
case X86::VRNDSCALESSZrri_Int:
case X86::VRNDSCALESSZrri_Intk:
case X86::VRNDSCALESSZrri_Intkz:
case X86::VRSQRT14SSZrr:
case X86::VRSQRT14SSZrrk:
case X86::VRSQRT14SSZrrkz:
Expand Down Expand Up @@ -7959,9 +7959,9 @@ static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
case X86::VREDUCESDZrri:
case X86::VREDUCESDZrrik:
case X86::VREDUCESDZrrikz:
case X86::VRNDSCALESDZr_Int:
case X86::VRNDSCALESDZr_Intk:
case X86::VRNDSCALESDZr_Intkz:
case X86::VRNDSCALESDZrri_Int:
case X86::VRNDSCALESDZrri_Intk:
case X86::VRNDSCALESDZrri_Intkz:
case X86::VRSQRT14SDZrr:
case X86::VRSQRT14SDZrrk:
case X86::VRSQRT14SDZrrkz:
Expand Down
18 changes: 9 additions & 9 deletions llvm/lib/Target/X86/X86SchedSapphireRapids.td
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Original file line number Diff line number Diff line change
Expand Up @@ -2300,8 +2300,8 @@ def : InstRW<[SPRWriteResGroup218, ReadAfterVecXLd], (instregex "^(V?)ROUNDS(D|S
"^VRNDSCALEP(D|S)Z128rm(bi|ik)$",
"^VRNDSCALEP(D|S)Z128rmbik(z?)$",
"^VRNDSCALEP(D|S)Z128rmi((kz)?)$",
"^VRNDSCALES(D|S)Zm$",
"^VRNDSCALES(D|S)Zm_Int((k|kz)?)$")>;
"^VRNDSCALES(D|S)Zrmi$",
"^VRNDSCALES(D|S)Zrmi_Int((k|kz)?)$")>;

def SPRWriteResGroup219 : SchedWriteRes<[SPRPort00_01]> {
let ReleaseAtCycles = [2];
Expand All @@ -2312,8 +2312,8 @@ def : InstRW<[SPRWriteResGroup219], (instregex "^(V?)ROUND(PD|SS)ri$",
"^(V?)ROUND(PS|SD)ri$",
"^(V?)ROUNDS(D|S)ri_Int$",
"^VRNDSCALEP(D|S)Z(128|256)rri((k|kz)?)$",
"^VRNDSCALES(D|S)Zr$",
"^VRNDSCALES(D|S)Zr(b?)_Int((k|kz)?)$",
"^VRNDSCALES(D|S)Zrri$",
"^VRNDSCALES(D|S)Zrri(b?)_Int((k|kz)?)$",
"^VROUNDP(D|S)Yri$")>;

def SPRWriteResGroup220 : SchedWriteRes<[SPRPort00_06]> {
Expand Down Expand Up @@ -3747,7 +3747,7 @@ def : InstRW<[SPRWriteResGroup390, ReadAfterVecXLd], (instregex "^VF(C?)MADDCSHZ
"^VF(C?)MULCPHZ128rm(b?)$",
"^VF(C?)MULCSHZrm$",
"^VRNDSCALEPHZ128rm(b?)i$",
"^VRNDSCALESHZm((_Int)?)$",
"^VRNDSCALESHZrmi((_Int)?)$",
"^VSCALEFPHZ128rm(b?)$")>;
def : InstRW<[SPRWriteResGroup390, ReadAfterVecYLd], (instregex "^VF(C?)MULCPHZ256rm(b?)$",
"^VRNDSCALEP(D|H|S)Z256rm(b?)i$",
Expand Down Expand Up @@ -3779,9 +3779,9 @@ def : InstRW<[SPRWriteResGroup392], (instregex "^VF(C?)MADDCPHZ(128|256)r$",
"^VF(C?)MULCPHZ(128|256)rr$",
"^VF(C?)MULCSHZrr(b?)$",
"^VRNDSCALEPHZ(128|256)rri$",
"^VRNDSCALESHZr(b?)_Int$",
"^VRNDSCALESHZrri(b?)_Int$",
"^VSCALEFPHZ(128|256)rr$")>;
def : InstRW<[SPRWriteResGroup392], (instrs VRNDSCALESHZr,
def : InstRW<[SPRWriteResGroup392], (instrs VRNDSCALESHZrri,
VSCALEFSHZrr,
VSCALEFSHZrrb_Int)>;

Expand Down Expand Up @@ -4884,7 +4884,7 @@ def SPRWriteResGroup534 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11]> {
let NumMicroOps = 3;
}
def : InstRW<[SPRWriteResGroup534, ReadAfterVecXLd], (instregex "^VRNDSCALEPHZ128rm(b?)ik(z?)$",
"^VRNDSCALESHZm_Intk(z?)$",
"^VRNDSCALESHZrmi_Intk(z?)$",
"^VSCALEFPHZ128rm(bk|kz)$",
"^VSCALEFPHZ128rm(k|bkz)$")>;
def : InstRW<[SPRWriteResGroup534, ReadAfterVecYLd], (instregex "^VRNDSCALEPHZ256rm(b?)ik(z?)$",
Expand All @@ -4898,7 +4898,7 @@ def SPRWriteResGroup535 : SchedWriteRes<[SPRPort00_01]> {
let NumMicroOps = 2;
}
def : InstRW<[SPRWriteResGroup535], (instregex "^VRNDSCALEPHZ(128|256)rrik(z?)$",
"^VRNDSCALESHZr(b?)_Intk(z?)$",
"^VRNDSCALESHZrri(b?)_Intk(z?)$",
"^VSCALEFPHZ(128|256)rrk(z?)$",
"^VSCALEFSHZrrb_Intk(z?)$",
"^VSCALEFSHZrrk(z?)$")>;
Expand Down
80 changes: 40 additions & 40 deletions llvm/test/CodeGen/X86/evex-to-vex-compress.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -2309,21 +2309,21 @@ body: |
; CHECK: $xmm0 = VINSERTPSrri $xmm0, $xmm0, 1
$xmm0 = VINSERTPSZrri $xmm0, $xmm0, 1
; CHECK: $xmm0 = VROUNDSDmi $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
$xmm0 = VRNDSCALESDZm $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
$xmm0 = VRNDSCALESDZrmi $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
; CHECK: $xmm0 = VROUNDSDri $xmm0, $xmm1, 15, implicit $mxcsr
$xmm0 = VRNDSCALESDZr $xmm0, $xmm1, 15, implicit $mxcsr
$xmm0 = VRNDSCALESDZrri $xmm0, $xmm1, 15, implicit $mxcsr
; CHECK: $xmm0 = VROUNDSSmi $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
$xmm0 = VRNDSCALESSZm $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
$xmm0 = VRNDSCALESSZrmi $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
; CHECK: $xmm0 = VROUNDSSri $xmm0, $xmm1, 15, implicit $mxcsr
$xmm0 = VRNDSCALESSZr $xmm0, $xmm1, 15, implicit $mxcsr
$xmm0 = VRNDSCALESSZrri $xmm0, $xmm1, 15, implicit $mxcsr
; CHECK: $xmm0 = VROUNDSDmi_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
$xmm0 = VRNDSCALESDZm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
$xmm0 = VRNDSCALESDZrmi_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
; CHECK: $xmm0 = VROUNDSDri_Int $xmm0, $xmm1, 15, implicit $mxcsr
$xmm0 = VRNDSCALESDZr_Int $xmm0, $xmm1, 15, implicit $mxcsr
$xmm0 = VRNDSCALESDZrri_Int $xmm0, $xmm1, 15, implicit $mxcsr
; CHECK: $xmm0 = VROUNDSSmi_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
$xmm0 = VRNDSCALESSZm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
$xmm0 = VRNDSCALESSZrmi_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
; CHECK: $xmm0 = VROUNDSSri_Int $xmm0, $xmm1, 15, implicit $mxcsr
$xmm0 = VRNDSCALESSZr_Int $xmm0, $xmm1, 15, implicit $mxcsr
$xmm0 = VRNDSCALESSZrri_Int $xmm0, $xmm1, 15, implicit $mxcsr

RET64
...
Expand Down Expand Up @@ -4636,38 +4636,38 @@ body: |
VUCOMISSZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
; CHECK: VUCOMISSZrr $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr
VUCOMISSZrr $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr
; CHECK: $xmm16 = VRNDSCALESDZm $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
$xmm16 = VRNDSCALESDZm $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
; CHECK: $xmm16 = VRNDSCALESDZr $xmm16, $xmm1, 15, implicit $mxcsr
$xmm16 = VRNDSCALESDZr $xmm16, $xmm1, 15, implicit $mxcsr
; CHECK: $xmm16 = VRNDSCALESSZm $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
$xmm16 = VRNDSCALESSZm $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
; CHECK: $xmm16 = VRNDSCALESSZr $xmm16, $xmm1, 15, implicit $mxcsr
$xmm16 = VRNDSCALESSZr $xmm16, $xmm1, 15, implicit $mxcsr
; CHECK: $xmm16 = VRNDSCALESDZm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
$xmm16 = VRNDSCALESDZm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
; CHECK: $xmm16 = VRNDSCALESDZr_Int $xmm16, $xmm1, 15, implicit $mxcsr
$xmm16 = VRNDSCALESDZr_Int $xmm16, $xmm1, 15, implicit $mxcsr
; CHECK: $xmm16 = VRNDSCALESSZm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
$xmm16 = VRNDSCALESSZm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
; CHECK: $xmm16 = VRNDSCALESSZr_Int $xmm16, $xmm1, 15, implicit $mxcsr
$xmm16 = VRNDSCALESSZr_Int $xmm16, $xmm1, 15, implicit $mxcsr
; CHECK: $xmm0 = VRNDSCALESDZm $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
$xmm0 = VRNDSCALESDZm $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
; CHECK: $xmm0 = VRNDSCALESDZr $xmm0, $xmm1, 31, implicit $mxcsr
$xmm0 = VRNDSCALESDZr $xmm0, $xmm1, 31, implicit $mxcsr
; CHECK: $xmm0 = VRNDSCALESSZm $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
$xmm0 = VRNDSCALESSZm $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
; CHECK: $xmm0 = VRNDSCALESSZr $xmm0, $xmm1, 31, implicit $mxcsr
$xmm0 = VRNDSCALESSZr $xmm0, $xmm1, 31, implicit $mxcsr
; CHECK: $xmm0 = VRNDSCALESDZm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
$xmm0 = VRNDSCALESDZm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
; CHECK: $xmm0 = VRNDSCALESDZr_Int $xmm0, $xmm1, 31, implicit $mxcsr
$xmm0 = VRNDSCALESDZr_Int $xmm0, $xmm1, 31, implicit $mxcsr
; CHECK: $xmm0 = VRNDSCALESSZm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
$xmm0 = VRNDSCALESSZm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
; CHECK: $xmm0 = VRNDSCALESSZr_Int $xmm0, $xmm1, 31, implicit $mxcsr
$xmm0 = VRNDSCALESSZr_Int $xmm0, $xmm1, 31, implicit $mxcsr
; CHECK: $xmm16 = VRNDSCALESDZrmi $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
$xmm16 = VRNDSCALESDZrmi $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
; CHECK: $xmm16 = VRNDSCALESDZrri $xmm16, $xmm1, 15, implicit $mxcsr
$xmm16 = VRNDSCALESDZrri $xmm16, $xmm1, 15, implicit $mxcsr
; CHECK: $xmm16 = VRNDSCALESSZrmi $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
$xmm16 = VRNDSCALESSZrmi $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
; CHECK: $xmm16 = VRNDSCALESSZrri $xmm16, $xmm1, 15, implicit $mxcsr
$xmm16 = VRNDSCALESSZrri $xmm16, $xmm1, 15, implicit $mxcsr
; CHECK: $xmm16 = VRNDSCALESDZrmi_Int $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
$xmm16 = VRNDSCALESDZrmi_Int $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
; CHECK: $xmm16 = VRNDSCALESDZrri_Int $xmm16, $xmm1, 15, implicit $mxcsr
$xmm16 = VRNDSCALESDZrri_Int $xmm16, $xmm1, 15, implicit $mxcsr
; CHECK: $xmm16 = VRNDSCALESSZrmi_Int $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
$xmm16 = VRNDSCALESSZrmi_Int $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
; CHECK: $xmm16 = VRNDSCALESSZrri_Int $xmm16, $xmm1, 15, implicit $mxcsr
$xmm16 = VRNDSCALESSZrri_Int $xmm16, $xmm1, 15, implicit $mxcsr
; CHECK: $xmm0 = VRNDSCALESDZrmi $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
$xmm0 = VRNDSCALESDZrmi $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
; CHECK: $xmm0 = VRNDSCALESDZrri $xmm0, $xmm1, 31, implicit $mxcsr
$xmm0 = VRNDSCALESDZrri $xmm0, $xmm1, 31, implicit $mxcsr
; CHECK: $xmm0 = VRNDSCALESSZrmi $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
$xmm0 = VRNDSCALESSZrmi $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
; CHECK: $xmm0 = VRNDSCALESSZrri $xmm0, $xmm1, 31, implicit $mxcsr
$xmm0 = VRNDSCALESSZrri $xmm0, $xmm1, 31, implicit $mxcsr
; CHECK: $xmm0 = VRNDSCALESDZrmi_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
$xmm0 = VRNDSCALESDZrmi_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
; CHECK: $xmm0 = VRNDSCALESDZrri_Int $xmm0, $xmm1, 31, implicit $mxcsr
$xmm0 = VRNDSCALESDZrri_Int $xmm0, $xmm1, 31, implicit $mxcsr
; CHECK: $xmm0 = VRNDSCALESSZrmi_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
$xmm0 = VRNDSCALESSZrmi_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
; CHECK: $xmm0 = VRNDSCALESSZrri_Int $xmm0, $xmm1, 31, implicit $mxcsr
$xmm0 = VRNDSCALESSZrri_Int $xmm0, $xmm1, 31, implicit $mxcsr

RET64
...
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