AMDGPU: Pass HwMode to AMDGPUGenRegisterInfo

[arsenm]

I haven't figured out how to do anything useful with this yet,
but it seems you are supposed to pass this to the subtarget
constructor.

[arsenm]

• AMDGPU: Pass HwMode to AMDGPUGenRegisterInfo #117449 👈 (View in Graphite)
• main

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[llvmbot]

@llvm/pr-subscribers-backend-amdgpu

Author: Matt Arsenault (arsenm)

Changes

I haven't figured out how to do anything useful with this yet,
but it seems you are supposed to pass this to the subtarget
constructor.

---

Full diff: https://github.com/llvm/llvm-project/pull/117449.diff

1 Files Affected:

• (modified) llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp (+2-1)

diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 246ef7ad481ab7..049f4af4dd2f93 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -319,7 +319,8 @@ struct SGPRSpillBuilder {
 
 SIRegisterInfo::SIRegisterInfo(const GCNSubtarget &ST)
     : AMDGPUGenRegisterInfo(AMDGPU::PC_REG, ST.getAMDGPUDwarfFlavour(),
-                            ST.getAMDGPUDwarfFlavour()),
+                            ST.getAMDGPUDwarfFlavour(),
+                            /*PC=*/0, ST.getHwMode()),
       ST(ST), SpillSGPRToVGPR(EnableSpillSGPRToVGPR), isWave32(ST.isWave32()) {
 
   assert(getSubRegIndexLaneMask(AMDGPU::sub0).getAsInteger() == 3 &&

[shiltian]

seems not hurt anyway