[RISC-V] Fix incorrect epilogue_begin #120623
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@llvm/pr-subscribers-backend-msp430 @llvm/pr-subscribers-backend-risc-v Author: Venkata Ramanaiah Nalamothu (RamNalamothu) ChangesPatch is 143.26 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/120623.diff 61 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index 408adcd330b846..9b8fc2ef46afd7 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -1138,13 +1138,14 @@ class TargetInstrInfo : public MCInstrInfo {
/// register, \p VReg is the register being assigned. This additional register
/// argument is needed for certain targets when invoked from RegAllocFast to
/// map the spilled physical register to its virtual register. A null register
- /// can be passed elsewhere.
- virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- Register SrcReg, bool isKill, int FrameIndex,
- const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const {
+ /// can be passed elsewhere. The \p Flags is used to set appropriate machine
+ /// flags on the spill instruction e.g. FrameSetup flag on a callee saved
+ /// register spill instruction, part of prologue, during the frame lowering.
+ virtual void storeRegToStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
+ bool isKill, int FrameIndex, const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const {
llvm_unreachable("Target didn't implement "
"TargetInstrInfo::storeRegToStackSlot!");
}
@@ -1156,13 +1157,14 @@ class TargetInstrInfo : public MCInstrInfo {
/// register, \p VReg is the register being assigned. This additional register
/// argument is needed for certain targets when invoked from RegAllocFast to
/// map the loaded physical register to its virtual register. A null register
- /// can be passed elsewhere.
- virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- Register DestReg, int FrameIndex,
- const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const {
+ /// can be passed elsewhere. The \p Flags is used to set appropriate machine
+ /// flags on the spill instruction e.g. FrameDestroy flag on a callee saved
+ /// register reload instruction, part of epilogue, during the frame lowering.
+ virtual void loadRegFromStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg,
+ int FrameIndex, const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const {
llvm_unreachable("Target didn't implement "
"TargetInstrInfo::loadRegFromStackSlot!");
}
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index fd24e49f948a20..3af891b95fe3d3 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -5278,7 +5278,8 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
Register SrcReg, bool isKill, int FI,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI,
- Register VReg) const {
+ Register VReg,
+ MachineInstr::MIFlag Flags) const {
MachineFunction &MF = *MBB.getParent();
MachineFrameInfo &MFI = MF.getFrameInfo();
@@ -5445,12 +5446,10 @@ static void loadRegPairFromStackSlot(const TargetRegisterInfo &TRI,
.addMemOperand(MMO);
}
-void AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- Register DestReg, int FI,
- const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const {
+void AArch64InstrInfo::loadRegFromStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg,
+ int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
+ Register VReg, MachineInstr::MIFlag Flags) const {
MachineFunction &MF = *MBB.getParent();
MachineFrameInfo &MFI = MF.getFrameInfo();
MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(MF, FI);
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
index e37f70f7d985de..9a0034223ab9ba 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
@@ -347,18 +347,17 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
bool KillSrc, bool RenamableDest = false,
bool RenamableSrc = false) const override;
- void storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI, Register SrcReg,
- bool isKill, int FrameIndex,
- const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const override;
-
- void loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI, Register DestReg,
- int FrameIndex, const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const override;
+ void storeRegToStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
+ bool isKill, int FrameIndex, const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
+
+ void loadRegFromStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ Register DestReg, int FrameIndex, const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
// This tells target independent code that it is okay to pass instructions
// with subreg operands to foldMemoryOperandImpl.
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index f97ea40caa6704..8234e7d0af2529 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -1724,7 +1724,8 @@ static unsigned getVectorRegSpillSaveOpcode(Register Reg,
void SIInstrInfo::storeRegToStackSlot(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
bool isKill, int FrameIndex, const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI, Register VReg) const {
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags) const {
MachineFunction *MF = MBB.getParent();
SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
MachineFrameInfo &FrameInfo = MF->getFrameInfo();
@@ -1951,7 +1952,8 @@ void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
Register DestReg, int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI,
- Register VReg) const {
+ Register VReg,
+ MachineInstr::MIFlag Flags) const {
MachineFunction *MF = MBB.getParent();
SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
MachineFrameInfo &FrameInfo = MF->getFrameInfo();
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 8f9ca6141816d4..71a24b6061a698 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -278,18 +278,17 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
MachineBasicBlock::iterator I, const DebugLoc &DL,
Register SrcReg, int Value) const;
- void storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI, Register SrcReg,
- bool isKill, int FrameIndex,
- const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const override;
-
- void loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI, Register DestReg,
- int FrameIndex, const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const override;
+ void storeRegToStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
+ bool isKill, int FrameIndex, const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
+
+ void loadRegFromStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg,
+ int FrameIndex, const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
bool expandPostRAPseudo(MachineInstr &MI) const override;
diff --git a/llvm/lib/Target/ARC/ARCInstrInfo.cpp b/llvm/lib/Target/ARC/ARCInstrInfo.cpp
index 78db68fca3050a..aa30c8a2a96daf 100644
--- a/llvm/lib/Target/ARC/ARCInstrInfo.cpp
+++ b/llvm/lib/Target/ARC/ARCInstrInfo.cpp
@@ -294,7 +294,8 @@ void ARCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
void ARCInstrInfo::storeRegToStackSlot(
MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register SrcReg,
bool IsKill, int FrameIndex, const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI, Register VReg) const {
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags) const {
DebugLoc DL = MBB.findDebugLoc(I);
MachineFunction &MF = *MBB.getParent();
MachineFrameInfo &MFI = MF.getFrameInfo();
@@ -323,7 +324,8 @@ void ARCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
Register DestReg, int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI,
- Register VReg) const {
+ Register VReg,
+ MachineInstr::MIFlag Flags) const {
DebugLoc DL = MBB.findDebugLoc(I);
MachineFunction &MF = *MBB.getParent();
MachineFrameInfo &MFI = MF.getFrameInfo();
diff --git a/llvm/lib/Target/ARC/ARCInstrInfo.h b/llvm/lib/Target/ARC/ARCInstrInfo.h
index e25f9902522607..8861b4689925f2 100644
--- a/llvm/lib/Target/ARC/ARCInstrInfo.h
+++ b/llvm/lib/Target/ARC/ARCInstrInfo.h
@@ -68,18 +68,17 @@ class ARCInstrInfo : public ARCGenInstrInfo {
bool KillSrc, bool RenamableDest = false,
bool RenamableSrc = false) const override;
- void storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI, Register SrcReg,
- bool IsKill, int FrameIndex,
- const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const override;
-
- void loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI, Register DestReg,
- int FrameIndex, const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const override;
+ void storeRegToStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
+ bool IsKill, int FrameIndex, const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
+
+ void loadRegFromStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg,
+ int FrameIndex, const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
bool
reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index e3e2e83fd5c7eb..89abdb11595ab5 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -1118,7 +1118,8 @@ void ARMBaseInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
Register SrcReg, bool isKill, int FI,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI,
- Register VReg) const {
+ Register VReg,
+ MachineInstr::MIFlag Flags) const {
MachineFunction &MF = *MBB.getParent();
MachineFrameInfo &MFI = MF.getFrameInfo();
Align Alignment = MFI.getObjectAlign(FI);
@@ -1379,12 +1380,10 @@ Register ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
return false;
}
-void ARMBaseInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator I,
- Register DestReg, int FI,
- const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const {
+void ARMBaseInstrInfo::loadRegFromStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg,
+ int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
+ Register VReg, MachineInstr::MIFlag Flags) const {
DebugLoc DL;
if (I != MBB.end()) DL = I->getDebugLoc();
MachineFunction &MF = *MBB.getParent();
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
index b6f20e6f99a0a9..afe610a0d9dd73 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -212,18 +212,17 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
bool KillSrc, bool RenamableDest = false,
bool RenamableSrc = false) const override;
- void storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI, Register SrcReg,
- bool isKill, int FrameIndex,
- const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const override;
-
- void loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI, Register DestReg,
- int FrameIndex, const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const override;
+ void storeRegToStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
+ bool isKill, int FrameIndex, const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
+
+ void loadRegFromStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ Register DestReg, int FrameIndex, const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
bool expandPostRAPseudo(MachineInstr &MI) const override;
diff --git a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
index a38aa3de40d901..cf151e1f8458fb 100644
--- a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
@@ -117,7 +117,8 @@ void Thumb1InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
Register SrcReg, bool isKill, int FI,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI,
- Register VReg) const {
+ Register VReg,
+ MachineInstr::MIFlag Flags) const {
assert((RC == &ARM::tGPRRegClass ||
(SrcReg.isPhysical() && isARMLowRegister(SrcReg))) &&
"Unknown regclass!");
@@ -141,12 +142,10 @@ void Thumb1InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
}
}
-void Thumb1InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator I,
- Register DestReg, int FI,
- const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const {
+void Thumb1InstrInfo::loadRegFromStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg,
+ int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
+ Register VReg, MachineInstr::MIFlag Flags) const {
assert((RC->hasSuperClassEq(&ARM::tGPRRegClass) ||
(DestReg.isPhysical() && isARMLowRegister(DestReg))) &&
"Unknown regclass!");
diff --git a/llvm/lib/Target/ARM/Thumb1InstrInfo.h b/llvm/lib/Target/ARM/Thumb1InstrInfo.h
index 84241fb8a9a66b..b9eb58692bab06 100644
--- a/llvm/lib/Target/ARM/Thumb1InstrInfo.h
+++ b/llvm/lib/Target/ARM/Thumb1InstrInfo.h
@@ -41,18 +41,17 @@ class Thumb1InstrInfo : public ARMBaseInstrInfo {
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
bool KillSrc, bool RenamableDest = false,
bool RenamableSrc = false) const override;
- void storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI, Register SrcReg,
- bool isKill, int FrameIndex,
- const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const override;
-
- void loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI, Register DestReg,
- int FrameIndex, const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const override;
+ void storeRegToStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
+ bool isKill, int FrameIndex, const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
+
+ void loadRegFromStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ Register DestReg, int FrameIndex, const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
bool canCopyGluedNodeDuringSchedule(SDNode *N) c...
[truncated]
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@llvm/pr-subscribers-backend-sparc Author: Venkata Ramanaiah Nalamothu (RamNalamothu) ChangesPatch is 143.26 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/120623.diff 61 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index 408adcd330b846..9b8fc2ef46afd7 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -1138,13 +1138,14 @@ class TargetInstrInfo : public MCInstrInfo {
/// register, \p VReg is the register being assigned. This additional register
/// argument is needed for certain targets when invoked from RegAllocFast to
/// map the spilled physical register to its virtual register. A null register
- /// can be passed elsewhere.
- virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- Register SrcReg, bool isKill, int FrameIndex,
- const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const {
+ /// can be passed elsewhere. The \p Flags is used to set appropriate machine
+ /// flags on the spill instruction e.g. FrameSetup flag on a callee saved
+ /// register spill instruction, part of prologue, during the frame lowering.
+ virtual void storeRegToStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
+ bool isKill, int FrameIndex, const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const {
llvm_unreachable("Target didn't implement "
"TargetInstrInfo::storeRegToStackSlot!");
}
@@ -1156,13 +1157,14 @@ class TargetInstrInfo : public MCInstrInfo {
/// register, \p VReg is the register being assigned. This additional register
/// argument is needed for certain targets when invoked from RegAllocFast to
/// map the loaded physical register to its virtual register. A null register
- /// can be passed elsewhere.
- virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- Register DestReg, int FrameIndex,
- const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const {
+ /// can be passed elsewhere. The \p Flags is used to set appropriate machine
+ /// flags on the spill instruction e.g. FrameDestroy flag on a callee saved
+ /// register reload instruction, part of epilogue, during the frame lowering.
+ virtual void loadRegFromStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg,
+ int FrameIndex, const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const {
llvm_unreachable("Target didn't implement "
"TargetInstrInfo::loadRegFromStackSlot!");
}
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index fd24e49f948a20..3af891b95fe3d3 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -5278,7 +5278,8 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
Register SrcReg, bool isKill, int FI,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI,
- Register VReg) const {
+ Register VReg,
+ MachineInstr::MIFlag Flags) const {
MachineFunction &MF = *MBB.getParent();
MachineFrameInfo &MFI = MF.getFrameInfo();
@@ -5445,12 +5446,10 @@ static void loadRegPairFromStackSlot(const TargetRegisterInfo &TRI,
.addMemOperand(MMO);
}
-void AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- Register DestReg, int FI,
- const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const {
+void AArch64InstrInfo::loadRegFromStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg,
+ int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
+ Register VReg, MachineInstr::MIFlag Flags) const {
MachineFunction &MF = *MBB.getParent();
MachineFrameInfo &MFI = MF.getFrameInfo();
MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(MF, FI);
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
index e37f70f7d985de..9a0034223ab9ba 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
@@ -347,18 +347,17 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
bool KillSrc, bool RenamableDest = false,
bool RenamableSrc = false) const override;
- void storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI, Register SrcReg,
- bool isKill, int FrameIndex,
- const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const override;
-
- void loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI, Register DestReg,
- int FrameIndex, const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const override;
+ void storeRegToStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
+ bool isKill, int FrameIndex, const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
+
+ void loadRegFromStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ Register DestReg, int FrameIndex, const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
// This tells target independent code that it is okay to pass instructions
// with subreg operands to foldMemoryOperandImpl.
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index f97ea40caa6704..8234e7d0af2529 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -1724,7 +1724,8 @@ static unsigned getVectorRegSpillSaveOpcode(Register Reg,
void SIInstrInfo::storeRegToStackSlot(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
bool isKill, int FrameIndex, const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI, Register VReg) const {
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags) const {
MachineFunction *MF = MBB.getParent();
SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
MachineFrameInfo &FrameInfo = MF->getFrameInfo();
@@ -1951,7 +1952,8 @@ void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
Register DestReg, int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI,
- Register VReg) const {
+ Register VReg,
+ MachineInstr::MIFlag Flags) const {
MachineFunction *MF = MBB.getParent();
SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
MachineFrameInfo &FrameInfo = MF->getFrameInfo();
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 8f9ca6141816d4..71a24b6061a698 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -278,18 +278,17 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
MachineBasicBlock::iterator I, const DebugLoc &DL,
Register SrcReg, int Value) const;
- void storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI, Register SrcReg,
- bool isKill, int FrameIndex,
- const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const override;
-
- void loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI, Register DestReg,
- int FrameIndex, const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const override;
+ void storeRegToStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
+ bool isKill, int FrameIndex, const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
+
+ void loadRegFromStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg,
+ int FrameIndex, const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
bool expandPostRAPseudo(MachineInstr &MI) const override;
diff --git a/llvm/lib/Target/ARC/ARCInstrInfo.cpp b/llvm/lib/Target/ARC/ARCInstrInfo.cpp
index 78db68fca3050a..aa30c8a2a96daf 100644
--- a/llvm/lib/Target/ARC/ARCInstrInfo.cpp
+++ b/llvm/lib/Target/ARC/ARCInstrInfo.cpp
@@ -294,7 +294,8 @@ void ARCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
void ARCInstrInfo::storeRegToStackSlot(
MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register SrcReg,
bool IsKill, int FrameIndex, const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI, Register VReg) const {
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags) const {
DebugLoc DL = MBB.findDebugLoc(I);
MachineFunction &MF = *MBB.getParent();
MachineFrameInfo &MFI = MF.getFrameInfo();
@@ -323,7 +324,8 @@ void ARCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
Register DestReg, int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI,
- Register VReg) const {
+ Register VReg,
+ MachineInstr::MIFlag Flags) const {
DebugLoc DL = MBB.findDebugLoc(I);
MachineFunction &MF = *MBB.getParent();
MachineFrameInfo &MFI = MF.getFrameInfo();
diff --git a/llvm/lib/Target/ARC/ARCInstrInfo.h b/llvm/lib/Target/ARC/ARCInstrInfo.h
index e25f9902522607..8861b4689925f2 100644
--- a/llvm/lib/Target/ARC/ARCInstrInfo.h
+++ b/llvm/lib/Target/ARC/ARCInstrInfo.h
@@ -68,18 +68,17 @@ class ARCInstrInfo : public ARCGenInstrInfo {
bool KillSrc, bool RenamableDest = false,
bool RenamableSrc = false) const override;
- void storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI, Register SrcReg,
- bool IsKill, int FrameIndex,
- const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const override;
-
- void loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI, Register DestReg,
- int FrameIndex, const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const override;
+ void storeRegToStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
+ bool IsKill, int FrameIndex, const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
+
+ void loadRegFromStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg,
+ int FrameIndex, const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
bool
reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index e3e2e83fd5c7eb..89abdb11595ab5 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -1118,7 +1118,8 @@ void ARMBaseInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
Register SrcReg, bool isKill, int FI,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI,
- Register VReg) const {
+ Register VReg,
+ MachineInstr::MIFlag Flags) const {
MachineFunction &MF = *MBB.getParent();
MachineFrameInfo &MFI = MF.getFrameInfo();
Align Alignment = MFI.getObjectAlign(FI);
@@ -1379,12 +1380,10 @@ Register ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
return false;
}
-void ARMBaseInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator I,
- Register DestReg, int FI,
- const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const {
+void ARMBaseInstrInfo::loadRegFromStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg,
+ int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
+ Register VReg, MachineInstr::MIFlag Flags) const {
DebugLoc DL;
if (I != MBB.end()) DL = I->getDebugLoc();
MachineFunction &MF = *MBB.getParent();
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
index b6f20e6f99a0a9..afe610a0d9dd73 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -212,18 +212,17 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
bool KillSrc, bool RenamableDest = false,
bool RenamableSrc = false) const override;
- void storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI, Register SrcReg,
- bool isKill, int FrameIndex,
- const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const override;
-
- void loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI, Register DestReg,
- int FrameIndex, const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const override;
+ void storeRegToStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
+ bool isKill, int FrameIndex, const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
+
+ void loadRegFromStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ Register DestReg, int FrameIndex, const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
bool expandPostRAPseudo(MachineInstr &MI) const override;
diff --git a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
index a38aa3de40d901..cf151e1f8458fb 100644
--- a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
@@ -117,7 +117,8 @@ void Thumb1InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
Register SrcReg, bool isKill, int FI,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI,
- Register VReg) const {
+ Register VReg,
+ MachineInstr::MIFlag Flags) const {
assert((RC == &ARM::tGPRRegClass ||
(SrcReg.isPhysical() && isARMLowRegister(SrcReg))) &&
"Unknown regclass!");
@@ -141,12 +142,10 @@ void Thumb1InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
}
}
-void Thumb1InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator I,
- Register DestReg, int FI,
- const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const {
+void Thumb1InstrInfo::loadRegFromStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg,
+ int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
+ Register VReg, MachineInstr::MIFlag Flags) const {
assert((RC->hasSuperClassEq(&ARM::tGPRRegClass) ||
(DestReg.isPhysical() && isARMLowRegister(DestReg))) &&
"Unknown regclass!");
diff --git a/llvm/lib/Target/ARM/Thumb1InstrInfo.h b/llvm/lib/Target/ARM/Thumb1InstrInfo.h
index 84241fb8a9a66b..b9eb58692bab06 100644
--- a/llvm/lib/Target/ARM/Thumb1InstrInfo.h
+++ b/llvm/lib/Target/ARM/Thumb1InstrInfo.h
@@ -41,18 +41,17 @@ class Thumb1InstrInfo : public ARMBaseInstrInfo {
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
bool KillSrc, bool RenamableDest = false,
bool RenamableSrc = false) const override;
- void storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI, Register SrcReg,
- bool isKill, int FrameIndex,
- const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const override;
-
- void loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI, Register DestReg,
- int FrameIndex, const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const override;
+ void storeRegToStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
+ bool isKill, int FrameIndex, const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
+
+ void loadRegFromStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ Register DestReg, int FrameIndex, const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
bool canCopyGluedNodeDuringSchedule(SDNode *N) c...
[truncated]
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CC: @enoskova-sc does this interact with your shrinking wrapping patch? |
|
@topperc, this patch interacts with my shrink wrapping, but it addresses independent problem. |
|
Ping |
1 similar comment
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Ping |
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Can you split the interface change that affects every target into a separate from the RISCV specific change? |
It is already separate. This PR has two commits, one which makes the interface change and the other which uses the revised interface to fix RISC-V specific issue. Or are you suggesting making two PRs, one for the interface change and one for RISC-V specific fix? |
Make a separate PR. The github web interface won't let you push a PR as two separate commits. |
#120622 for the interface change. |
|
It seems like in general we cannot guarantee that prolog / epilog code is a contiguous region since instructions can be moved by optimisation. What is the solution in that case? Not saying we should address this in the PR, just wondering. |
mgudim
reviewed
Jan 21, 2025
mgudim
reviewed
Jan 21, 2025
topperc
reviewed
Jan 21, 2025
RamNalamothu
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I know the MachineScheduler excludes CFI_INSTRUCTION from its scheduling regions which prevents it moving instructions in the prolog/epilog. |
RamNalamothu
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All the code here that assumes prolog / epilog code i.e. CSR save / restore instructions is a contiguous region is part of the prologepilog pass alone. So, I think, we are good here. If we have to assume prolog / epilog code is not a contiguous region outside the prologepilog pass, then it's a concern for all the targets, not just for RISC-V / this patch, on how AsmPrinter is going to handle that while emitting prologue_end / epilogue_begin which, I think, can be discussed as a separate topic (?). |
|
Ping. I think I have addressed all the review comments. |
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can you please rebase on the latest main so we see this on top of #120622 |
Please add a commit message describing the problem and solution |
It's already rebased on to tip of main branch.
The commit message has the description 23768d5. I just didn't replicate that here on PR page and instead pointed to the issue #120553. |
The DwarfDebug.cpp implementation expects the epilogue instructions to have source location of last non-debug instruction after which the epilogue instructions are inserted. The epilogue_begin is set on location of the first FrameDestroy instruction with source line information that has been seen in the epilogue basic block. In the trunk, the risc-v backend sets the epilogue_begin after the epilogue has actually begun i.e. after callee saved register reloads and the source line information is not set on those reload instructions. This is leading to llvm#120553 where, while debugging, breaking on or single stepping to the epilogue_begin location will make accessing the variables from wrong place as the FP has been restored to the parent frame's FP. To fix that, this patch sets FrameSetup/FrameDestroy flags on the callee saved register spill/reload instructions which is actually correct. Then the RISCVInstrInfo::loadRegFromStackSlot uses FrameDestroy flag to identify a reload of the callee saved register in the epilogue and copies the source line information from insert position instruction to that reload instruction. Requires PR llvm#120622 Fixes llvm#120553
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lenary
reviewed
Jan 27, 2025
lenary
approved these changes
Jan 28, 2025
|
I will wait till end of the day for others who have commented and then merge, if I don't hear anything, so that the patch can go into the 20.x release branch. |
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/50/builds/9515 Here is the relevant piece of the build log for the reference |
|
FYI, it's not really helpful to wait from midnight US time until early morning US time; probably nobody saw your first message before you merged. If you actually want to give people time to comment, please give at least 24 hours. (In this case, I don't think you needed to wait anyway, so it's fine.) |
Thanks for the comments, @efriedma-quic. However, others who have commented on this patch, based on their comments' time, seems to be working in the closer time zone to mine and not in US time zone. |
|
The PR #120623 is a RISC-V target specific LLVM backend patch and is not related to Aarch64 / or any header file. So, this failure is not due to my patch.
From: LLVM Continuous Integration ***@***.***>
Sent: Tuesday, January 28, 2025 9:31 PM
To: llvm/llvm-project ***@***.***>
Cc: Ram Nalamothu (QUIC) ***@***.***>; State change ***@***.***>
Subject: Re: [llvm/llvm-project] [RISC-V] Fix incorrect epilogue_begin (PR #120623)
WARNING: This email originated from outside of Qualcomm. Please be wary of any links or attachments, and do not enable macros.
LLVM Buildbot has detected a new failure on builder flang-aarch64-dylib running on linaro-flang-aarch64-dylib while building llvm at step 5 "build-unified-tree".
Full details are available at: https://lab.llvm.org/buildbot/#/builders/50/builds/9515
Here is the relevant piece of the build log for the reference
Step 5 (build-unified-tree) failure: build (failure)
...
1211.283 [1279/1/5546] Building CXX object tools/mlir/lib/Target/LLVMIR/Dialect/GPU/CMakeFiles/obj.MLIRGPUToLLVMIRTranslation.dir/GPUToLLVMIRTranslation.cpp.o
1211.496 [1278/1/5547] Building CXX object tools/mlir/lib/Target/LLVMIR/Dialect/AMX/CMakeFiles/obj.MLIRAMXToLLVMIRTranslation.dir/AMXToLLVMIRTranslation.cpp.o
1211.646 [1277/1/5548] Building CXX object tools/mlir/lib/Target/LLVMIR/Dialect/Builtin/CMakeFiles/obj.MLIRBuiltinToLLVMIRTranslation.dir/BuiltinToLLVMIRTranslation.cpp.o
1211.779 [1276/1/5549] Building CXX object tools/mlir/lib/Target/LLVMIR/Dialect/NVVM/CMakeFiles/obj.MLIRLLVMIRToNVVMTranslation.dir/LLVMIRToNVVMTranslation.cpp.o
1211.896 [1275/1/5550] Building CXX object tools/mlir/lib/Target/LLVMIR/Dialect/LLVMIR/CMakeFiles/obj.MLIRLLVMIRToLLVMTranslation.dir/LLVMIRToLLVMTranslation.cpp.o
1212.041 [1274/1/5551] Building CXX object tools/mlir/lib/Target/LLVMIR/Dialect/LLVMIR/CMakeFiles/obj.MLIRLLVMToLLVMIRTranslation.dir/LLVMToLLVMIRTranslation.cpp.o
1212.198 [1273/1/5552] Building CXX object tools/mlir/lib/Target/LLVMIR/Dialect/OpenACC/CMakeFiles/obj.MLIROpenACCToLLVMIRTranslation.dir/OpenACCToLLVMIRTranslation.cpp.o
1212.372 [1272/1/5553] Building CXX object tools/mlir/lib/Target/LLVMIR/Dialect/ROCDL/CMakeFiles/obj.MLIRROCDLToLLVMIRTranslation.dir/ROCDLToLLVMIRTranslation.cpp.o
1212.494 [1271/1/5554] Building CXX object tools/mlir/test/lib/IR/CMakeFiles/MLIRTestIR.dir/TestPrintNesting.cpp.o
1225.172 [1270/1/5555] Building CXX object tools/mlir/test/lib/IR/CMakeFiles/MLIRTestIR.dir/TestSideEffects.cpp.o
FAILED: tools/mlir/test/lib/IR/CMakeFiles/MLIRTestIR.dir/TestSideEffects.cpp.o
/usr/local/bin/c++ -DGTEST_HAS_RTTI=0 -DMLIR_INCLUDE_TESTS -D_DEBUG -D_GLIBCXX_ASSERTIONS -D_GNU_SOURCE -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -I/home/tcwg-buildbot/worker/flang-aarch64-dylib/build/tools/mlir/test/lib/IR -I/home/tcwg-buildbot/worker/flang-aarch64-dylib/llvm-project/mlir/test/lib/IR -I/home/tcwg-buildbot/worker/flang-aarch64-dylib/build/tools/mlir/include -I/home/tcwg-buildbot/worker/flang-aarch64-dylib/llvm-project/mlir/include -I/home/tcwg-buildbot/worker/flang-aarch64-dylib/build/include -I/home/tcwg-buildbot/worker/flang-aarch64-dylib/llvm-project/llvm/include -I/home/tcwg-buildbot/worker/flang-aarch64-dylib/llvm-project/mlir/test/lib/IR/../Dialect/Test -I/home/tcwg-buildbot/worker/flang-aarch64-dylib/build/tools/mlir/test/lib/IR/../Dialect/Test -fPIC -fno-semantic-interposition -fvisibility-inlines-hidden -Werror=date-time -Werror=unguarded-availability-new -Wall -Wextra -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wmissing-field-initializers -pedantic -Wno-long-long -Wc++98-compat-extra-semi -Wimplicit-fallthrough -Wcovered-switch-default -Wno-noexcept-type -Wnon-virtual-dtor -Wdelete-non-virtual-dtor -Wsuggest-override -Wstring-conversion -Wmisleading-indentation -Wctad-maybe-unsupported -fdiagnostics-color -ffunction-sections -fdata-sections -Wundef -Werror=mismatched-tags -O3 -DNDEBUG -std=c++17 -fno-exceptions -funwind-tables -fno-rtti -UNDEBUG -MD -MT tools/mlir/test/lib/IR/CMakeFiles/MLIRTestIR.dir/TestSideEffects.cpp.o -MF tools/mlir/test/lib/IR/CMakeFiles/MLIRTestIR.dir/TestSideEffects.cpp.o.d -o tools/mlir/test/lib/IR/CMakeFiles/MLIRTestIR.dir/TestSideEffects.cpp.o -c /home/tcwg-buildbot/worker/flang-aarch64-dylib/llvm-project/mlir/test/lib/IR/TestSideEffects.cpp
In file included from /home/tcwg-buildbot/worker/flang-aarch64-dylib/llvm-project/mlir/test/lib/IR/TestSideEffects.cpp:9:
/home/tcwg-buildbot/worker/flang-aarch64-dylib/llvm-project/mlir/test/lib/IR/../Dialect/Test/TestOps.h:148:10: fatal error: 'TestOps.h.inc' file not found
148 | #include "TestOps.h.inc"
| ^~~~~~~~~~~~~~~
1 error generated.
ninja: build stopped: subcommand failed.
—
Reply to this email directly, view it on GitHub<#120623 (comment)>, or unsubscribe<https://github.com/notifications/unsubscribe-auth/AOVDB4CAVJWZXZ5GKAMKR4T2M6STRAVCNFSM6AAAAABT5UPZ6KVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZDMMJZGQYTINJZGI>.
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This patch resolves #120553