[AMDGPU][NFC] Move isXDL and isDGEMM to SIInstrInfo. #129103
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@llvm/pr-subscribers-backend-amdgpu Author: None (sstipano) ChangesFull diff: https://github.com/llvm/llvm-project/pull/129103.diff 3 Files Affected:
diff --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
index 1ff75095b220a..c1b64d707b632 100644
--- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
@@ -111,25 +111,6 @@ static bool isSMovRel(unsigned Opcode) {
}
}
-static bool isDGEMM(unsigned Opcode) {
- return AMDGPU::getMAIIsDGEMM(Opcode);
-}
-
-static bool isXDL(const GCNSubtarget &ST, const MachineInstr &MI) {
- unsigned Opcode = MI.getOpcode();
-
- if (!SIInstrInfo::isMAI(MI) ||
- isDGEMM(Opcode) ||
- Opcode == AMDGPU::V_ACCVGPR_WRITE_B32_e64 ||
- Opcode == AMDGPU::V_ACCVGPR_READ_B32_e64)
- return false;
-
- if (!ST.hasGFX940Insts())
- return true;
-
- return AMDGPU::getMAIIsGFX940XDL(Opcode);
-}
-
static bool isSendMsgTraceDataOrGDS(const SIInstrInfo &TII,
const MachineInstr &MI) {
if (TII.isAlwaysGDS(MI.getOpcode()))
@@ -2375,7 +2356,7 @@ int GCNHazardRecognizer::checkMAIHazards90A(MachineInstr *MI) {
unsigned Opc1 = MI1->getOpcode();
int NeedWaitStates = 0;
if (OpNo == SrcCIdx) {
- if (!isDGEMM(Opc) && (!ST.hasGFX940Insts() && isDGEMM(Opc1))) {
+ if (!SIInstrInfo::isDGEMM(Opc) && (!ST.hasGFX940Insts() && SIInstrInfo::isDGEMM(Opc1))) {
NeedWaitStates = 0;
} else if (FullReg) {
if ((Opc == AMDGPU::V_MFMA_F64_4X4X4F64_e64 ||
@@ -2392,7 +2373,7 @@ int GCNHazardRecognizer::checkMAIHazards90A(MachineInstr *MI) {
case AMDGPU::V_MFMA_F64_16X16X4F64_vgprcd_e64:
case AMDGPU::V_MFMA_F64_16X16X4F64_mac_e64:
case AMDGPU::V_MFMA_F64_16X16X4F64_mac_vgprcd_e64:
- if (!isXDL(ST, *MI))
+ if (!TII.isXDL(*MI))
NeedWaitStates =
ST.hasGFX950Insts()
? GFX950_DMFMA16x16WritesVGPROverlappedSrcCWaitStates
@@ -2400,18 +2381,18 @@ int GCNHazardRecognizer::checkMAIHazards90A(MachineInstr *MI) {
break;
case AMDGPU::V_MFMA_F64_4X4X4F64_e64:
case AMDGPU::V_MFMA_F64_4X4X4F64_vgprcd_e64:
- if (!isXDL(ST, *MI))
+ if (!TII.isXDL(*MI))
NeedWaitStates = DMFMA4x4WritesVGPROverlappedSrcCWaitStates;
break;
default:
int NumPasses = TSchedModel.computeInstrLatency(MI1);
if (ST.hasGFX940Insts()) {
- if (isXDL(ST, *MI) && !isXDL(ST, *MI1))
+ if (TII.isXDL(*MI) && !TII.isXDL(*MI1))
break;
NeedWaitStates =
- isXDL(ST, *MI1)
- ? (isXDL(ST, *MI)
+ TII.isXDL(*MI1)
+ ? (TII.isXDL(*MI)
? GFX940_XDL_N_PassWritesVGPROverlappedXDLOrSMFMASrcCWaitStates(
NumPasses, ST.hasGFX950Insts())
: GFX940_XDL_N_PassWritesVGPROverlappedSGEMMDGEMMSrcCWaitStates(
@@ -2424,18 +2405,18 @@ int GCNHazardRecognizer::checkMAIHazards90A(MachineInstr *MI) {
switch (NumPasses) {
case 2:
NeedWaitStates =
- isDGEMM(Opc) ? SMFMA4x4WritesVGPROverlappedDMFMASrcCWaitStates
+ SIInstrInfo::isDGEMM(Opc) ? SMFMA4x4WritesVGPROverlappedDMFMASrcCWaitStates
: SMFMA4x4WritesVGPROverlappedSMFMASrcCWaitStates;
break;
case 8:
NeedWaitStates =
- isDGEMM(Opc)
+ SIInstrInfo::isDGEMM(Opc)
? SMFMA16x16WritesVGPROverlappedDMFMASrcCWaitStates
: SMFMA16x16WritesVGPROverlappedSMFMASrcCWaitStates;
break;
case 16:
NeedWaitStates =
- isDGEMM(Opc)
+ SIInstrInfo::isDGEMM(Opc)
? SMFMA32x32WritesVGPROverlappedDMFMASrcCWaitStates
: SMFMA32x32WritesVGPROverlappedSMFMASrcCWaitStates;
break;
@@ -2464,7 +2445,7 @@ int GCNHazardRecognizer::checkMAIHazards90A(MachineInstr *MI) {
if (ST.hasGFX940Insts()) {
NeedWaitStates =
- isXDL(ST, *MI1)
+ TII.isXDL(*MI1)
? GFX940_XDL_N_PassWritesVGPROverlappedSrcABWaitStates(
NumPasses, ST.hasGFX950Insts())
: GFX940_SMFMA_N_PassWritesVGPROverlappedSrcABWaitStates(
@@ -2631,7 +2612,7 @@ int GCNHazardRecognizer::checkMAIVALUHazards(MachineInstr *MI) {
return 0;
auto IsDGEMMFn = [](const MachineInstr &MI) -> bool {
- return isDGEMM(MI.getOpcode());
+ return SIInstrInfo::isDGEMM(MI.getOpcode());
};
// This is checked in checkMAIHazards90A()
@@ -2670,7 +2651,7 @@ int GCNHazardRecognizer::checkMAIVALUHazards(MachineInstr *MI) {
bool DGEMMAfterVALUWrite = false;
auto IsDGEMMHazard = [&DGEMMAfterVALUWrite, this](const MachineInstr &MI) {
// Found DGEMM on reverse traversal to def.
- if (isDGEMM(MI.getOpcode()))
+ if (SIInstrInfo::isDGEMM(MI.getOpcode()))
DGEMMAfterVALUWrite = true;
// Only hazard if register is defined by a VALU and a DGEMM is found after
@@ -2745,7 +2726,7 @@ int GCNHazardRecognizer::checkMAIVALUHazards(MachineInstr *MI) {
int NumPasses = HazardDefLatency;
int NeedWaitStates = MaxWaitStates;
- if (isDGEMM(MFMA->getOpcode())) {
+ if (SIInstrInfo::isDGEMM(MFMA->getOpcode())) {
switch (HazardDefLatency) {
case 4:
NeedWaitStates = IsMemOrExport ? DMFMA4x4WriteVgprMemExpReadWaitStates
@@ -2765,7 +2746,7 @@ int GCNHazardRecognizer::checkMAIVALUHazards(MachineInstr *MI) {
}
} else if (ST.hasGFX940Insts()) {
NeedWaitStates =
- isXDL(ST, *MFMA)
+ TII.isXDL(*MFMA)
? GFX940_XDL_N_PassWriteVgprVALUMemExpReadWaitStates(
NumPasses, ST.hasGFX950Insts())
: GFX940_SMFMA_N_PassWriteVgprVALUMemExpReadWaitStates(
@@ -2838,7 +2819,7 @@ int GCNHazardRecognizer::checkMAIVALUHazards(MachineInstr *MI) {
int NeedWaitStates = MaxWaitStates;
int NumPasses = TSchedModel.computeInstrLatency(MFMA);
- if (isDGEMM(MFMA->getOpcode())) {
+ if (SIInstrInfo::isDGEMM(MFMA->getOpcode())) {
switch (NumPasses) {
case 4:
NeedWaitStates = DMFMA4x4WriteVgprVALUWriteWaitStates;
@@ -2852,7 +2833,7 @@ int GCNHazardRecognizer::checkMAIVALUHazards(MachineInstr *MI) {
}
} else if (ST.hasGFX940Insts()) {
NeedWaitStates =
- isXDL(ST, *MFMA)
+ TII.isXDL(*MFMA)
? GFX940_XDL_N_PassWriteVgprVALUWawWaitStates(
NumPasses, ST.hasGFX950Insts())
: GFX940_SMFMA_N_PassWriteVgprVALUWawWaitStates(NumPasses);
@@ -2880,11 +2861,11 @@ int GCNHazardRecognizer::checkMAIVALUHazards(MachineInstr *MI) {
}
auto IsSMFMAReadAsCFn = [&Reg, &MFMA, this](const MachineInstr &MI) {
- if (!SIInstrInfo::isMFMA(MI) || isDGEMM(MI.getOpcode()) ||
+ if (!SIInstrInfo::isMFMA(MI) || SIInstrInfo::isDGEMM(MI.getOpcode()) ||
!MI.readsRegister(Reg, &TRI))
return false;
- if (ST.hasGFX940Insts() && !isXDL(ST, MI))
+ if (ST.hasGFX940Insts() && !TII.isXDL(MI))
return false;
const MachineOperand *SrcC =
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 9aec2bef0c18a..7c9a540a44ce6 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -10251,3 +10251,18 @@ bool SIInstrInfo::isGlobalMemoryObject(const MachineInstr *MI) const {
return TargetInstrInfo::isGlobalMemoryObject(MI);
}
+
+bool SIInstrInfo::isXDL(const MachineInstr &MI) const {
+ unsigned Opcode = MI.getOpcode();
+
+ if (!SIInstrInfo::isMAI(MI) ||
+ isDGEMM(Opcode) ||
+ Opcode == AMDGPU::V_ACCVGPR_WRITE_B32_e64 ||
+ Opcode == AMDGPU::V_ACCVGPR_READ_B32_e64)
+ return false;
+
+ if (!ST.hasGFX940Insts())
+ return true;
+
+ return AMDGPU::getMAIIsGFX940XDL(Opcode);
+}
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 428322a5a2f04..30168e930b63e 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -847,6 +847,12 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return get(Opcode).TSFlags & SIInstrFlags::IsDOT;
}
+ bool isXDL(const MachineInstr &MI) const;
+
+ static bool isDGEMM(unsigned Opcode) {
+ return AMDGPU::getMAIIsDGEMM(Opcode);
+ }
+
static bool isLDSDIR(const MachineInstr &MI) {
return MI.getDesc().TSFlags & SIInstrFlags::LDSDIR;
}
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rampitec
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Feb 27, 2025
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/190/builds/15414 Here is the relevant piece of the build log for the reference |
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