[MIPS] Add MIPS i6400 and i6500 processors #130587

mgoudar · 2025-03-10T12:03:49Z

The i6400 and i6500 are high performance multi-core microprocessors from MIPS that provide best in class power efficiency for use in system-on-chip (SoC) applications. i6400 and i6500 implements Release 6 of the MIPS64 Instruction Set Architecture with full hardware multithreading and hardware virtualization support.

Scheduling model shall be added in separate commit/PR.

The i6400 and i6500 are high performance multi-core microprocessors from MIPS that provide best in class power efficiency for use in system-on-chip (SoC) applications. i6400 and i6500 implements Release 6 of the MIPS64 Instruction Set Architecture with full hardware multithreading and hardware virtualization support. Scheduling model shall be added in separate commit/PR.

github-actions · 2025-03-10T12:04:07Z

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llvmbot · 2025-03-10T12:04:40Z

@llvm/pr-subscribers-clang-driver

Author: Mallikarjuna Gouda (mgoudar)

Changes

The i6400 and i6500 are high performance multi-core microprocessors from MIPS that provide best in class power efficiency for use in system-on-chip (SoC) applications. i6400 and i6500 implements Release 6 of the MIPS64 Instruction Set Architecture with full hardware multithreading and hardware virtualization support.

Scheduling model shall be added in separate commit/PR.

Full diff: https://github.com/llvm/llvm-project/pull/130587.diff

7 Files Affected:

(modified) clang/lib/Basic/Targets/Mips.cpp (+3-1)
(modified) clang/lib/Driver/ToolChains/Arch/Mips.cpp (+4)
(modified) clang/lib/Driver/ToolChains/Gnu.cpp (+3-1)
(modified) clang/test/Driver/mips-abi.c (+24)
(modified) llvm/docs/ReleaseNotes.md (+2)
(modified) llvm/lib/Target/Mips/Mips.td (+10)
(modified) llvm/lib/Target/Mips/MipsSubtarget.h (+1-1)

diff --git a/clang/lib/Basic/Targets/Mips.cpp b/clang/lib/Basic/Targets/Mips.cpp
index 866be53c8a363..08f9e3c29d1ed 100644
--- a/clang/lib/Basic/Targets/Mips.cpp
+++ b/clang/lib/Basic/Targets/Mips.cpp
@@ -47,6 +47,8 @@ bool MipsTargetInfo::processorSupportsGPR64() const {
       .Case("mips64r6", true)
       .Case("octeon", true)
       .Case("octeon+", true)
+      .Case("i6400", true)
+      .Case("i6500", true)
       .Default(false);
 }
 
@@ -54,7 +56,7 @@ static constexpr llvm::StringLiteral ValidCPUNames[] = {
     {"mips1"},  {"mips2"},    {"mips3"},    {"mips4"},    {"mips5"},
     {"mips32"}, {"mips32r2"}, {"mips32r3"}, {"mips32r5"}, {"mips32r6"},
     {"mips64"}, {"mips64r2"}, {"mips64r3"}, {"mips64r5"}, {"mips64r6"},
-    {"octeon"}, {"octeon+"}, {"p5600"}};
+    {"octeon"}, {"octeon+"},  {"p5600"},    {"i6400"},    {"i6500"}};
 
 bool MipsTargetInfo::isValidCPUName(StringRef Name) const {
   return llvm::is_contained(ValidCPUNames, Name);
diff --git a/clang/lib/Driver/ToolChains/Arch/Mips.cpp b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
index ca0745fc2b32d..9c817f238524c 100644
--- a/clang/lib/Driver/ToolChains/Arch/Mips.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
@@ -104,6 +104,8 @@ void mips::getMipsCPUAndABI(const ArgList &Args, const llvm::Triple &Triple,
                   .Case("mips64r6", "n64")
                   .Case("octeon", "n64")
                   .Case("p5600", "o32")
+                  .Case("i6400", "n64")
+                  .Case("i6500", "n64")
                   .Default("");
   }
 
@@ -514,5 +516,7 @@ bool mips::supportsIndirectJumpHazardBarrier(StringRef &CPU) {
       .Case("mips64r6", true)
       .Case("octeon", true)
       .Case("p5600", true)
+      .Case("i6400", true)
+      .Case("i6500", true)
       .Default(false);
 }
diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp b/clang/lib/Driver/ToolChains/Gnu.cpp
index f56eeda3cb5f6..68c288f516fba 100644
--- a/clang/lib/Driver/ToolChains/Gnu.cpp
+++ b/clang/lib/Driver/ToolChains/Gnu.cpp
@@ -1501,7 +1501,9 @@ bool clang::driver::findMIPSMultilibs(const Driver &D,
                       CPUName == "mips64r5" || CPUName == "octeon" ||
                       CPUName == "octeon+",
                   "-march=mips64r2", Flags);
-  addMultilibFlag(CPUName == "mips64r6", "-march=mips64r6", Flags);
+  addMultilibFlag(CPUName == "mips64r6" || CPUName == "i6400" ||
+                      CPUName == "i6500",
+                  "-march=mips64r6", Flags);
   addMultilibFlag(isMicroMips(Args), "-mmicromips", Flags);
   addMultilibFlag(tools::mips::isUCLibc(Args), "-muclibc", Flags);
   addMultilibFlag(tools::mips::isNaN2008(D, Args, TargetTriple), "-mnan=2008",
diff --git a/clang/test/Driver/mips-abi.c b/clang/test/Driver/mips-abi.c
index 06570b50928a1..9a2180c516a61 100644
--- a/clang/test/Driver/mips-abi.c
+++ b/clang/test/Driver/mips-abi.c
@@ -121,6 +121,30 @@
 // MIPS-ARCH-P5600-N64: error: ABI 'n64' is not supported on CPU 'p5600'
 //
 // RUN: %clang --target=mips-linux-gnu -### -c %s \
+// RUN:        -march=i6400 2>&1 \
+// RUN:   | FileCheck -check-prefix=MIPS-ARCH-I6400 %s
+// MIPS-ARCH-I6400: "-target-cpu" "i6400"
+// MIPS-ARCH-I6400: "-target-abi" "o32"
+//
+// RUN: %clang --target=mips-linux-gnu -### -c %s \
+// RUN:        -march=i6400 -mabi=64 2>&1 \
+// RUN:   | FileCheck -check-prefix=MIPS-ARCH-I6400-N64 %s
+// MIPS-ARCH-I6400-N64: "-target-cpu" "i6400"
+// MIPS-ARCH-I6400-N64: "-target-abi" "n64"
+//
+// RUN: %clang --target=mips-linux-gnu -### -c %s \
+// RUN:        -march=i6500 2>&1 \
+// RUN:   | FileCheck -check-prefix=MIPS-ARCH-I6500 %s
+// MIPS-ARCH-I6500: "-target-cpu" "i6500"
+// MIPS-ARCH-I6500: "-target-abi" "o32"
+//
+// RUN: %clang --target=mips-linux-gnu -### -c %s \
+// RUN:        -march=i6500 -mabi=64 2>&1 \
+// RUN:   | FileCheck -check-prefix=MIPS-ARCH-I6500-N64 %s
+// MIPS-ARCH-I6500-N64: "-target-cpu" "i6500"
+// MIPS-ARCH-I6500-N64: "-target-abi" "n64"
+//
+// RUN: %clang --target=mips-linux-gnu -### -c %s \
 // RUN:        -march=mips64 2>&1 \
 // RUN:   | FileCheck -check-prefix=MIPS-ARCH-3264 %s
 // MIPS-ARCH-3264: "-target-cpu" "mips64"
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index d7a80ae93aa34..d23019785e33d 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -101,6 +101,8 @@ Changes to the LoongArch Backend
 Changes to the MIPS Backend
 ---------------------------
 
+* `-mcpu=i6400` and `-mcpu=i6500` was added.
+
 Changes to the PowerPC Backend
 ------------------------------
 
diff --git a/llvm/lib/Target/Mips/Mips.td b/llvm/lib/Target/Mips/Mips.td
index 923e0c9cdde75..15e510ee263bc 100644
--- a/llvm/lib/Target/Mips/Mips.td
+++ b/llvm/lib/Target/Mips/Mips.td
@@ -238,6 +238,14 @@ def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl",
                                  "MipsSubtarget::CPU::P5600",
                                  "The P5600 Processor", [FeatureMips32r5]>;
 
+def ImplI6400
+    : SubtargetFeature<"i6400", "ProcImpl", "MipsSubtarget::CPU::I6400",
+                       "The I6400 Processor", [FeatureMips64r6]>;
+
+def ImplI6500
+    : SubtargetFeature<"i6500", "ProcImpl", "MipsSubtarget::CPU::I6400",
+                       "The I6500 Processor", [FeatureMips64r6]>;
+
 class Proc<string Name, list<SubtargetFeature> Features>
  : ProcessorModel<Name, MipsGenericModel, Features>;
 
@@ -261,6 +269,8 @@ def : Proc<"mips64r6", [FeatureMips64r6]>;
 def : Proc<"octeon", [FeatureMips64r2, FeatureCnMips]>;
 def : Proc<"octeon+", [FeatureMips64r2, FeatureCnMips, FeatureCnMipsP]>;
 def : ProcessorModel<"p5600", MipsP5600Model, [ImplP5600]>;
+def : ProcessorModel<"i6400", NoSchedModel, [ImplI6400]>;
+def : ProcessorModel<"i6500", NoSchedModel, [ImplI6500]>;
 
 def MipsAsmParser : AsmParser {
   let ShouldEmitMatchRegisterName = 0;
diff --git a/llvm/lib/Target/Mips/MipsSubtarget.h b/llvm/lib/Target/Mips/MipsSubtarget.h
index 85cf45d4702ae..0c75597d3decf 100644
--- a/llvm/lib/Target/Mips/MipsSubtarget.h
+++ b/llvm/lib/Target/Mips/MipsSubtarget.h
@@ -43,7 +43,7 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
     Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
   };
 
-  enum class CPU { P5600 };
+  enum class CPU { P5600, I6400 };
 
   // Used to avoid printing dsp warnings multiple times.
   static bool DspWarningPrinted;

llvmbot · 2025-03-10T12:04:40Z

@llvm/pr-subscribers-clang

Author: Mallikarjuna Gouda (mgoudar)

Changes

The i6400 and i6500 are high performance multi-core microprocessors from MIPS that provide best in class power efficiency for use in system-on-chip (SoC) applications. i6400 and i6500 implements Release 6 of the MIPS64 Instruction Set Architecture with full hardware multithreading and hardware virtualization support.

Scheduling model shall be added in separate commit/PR.

Full diff: https://github.com/llvm/llvm-project/pull/130587.diff

7 Files Affected:

(modified) clang/lib/Basic/Targets/Mips.cpp (+3-1)
(modified) clang/lib/Driver/ToolChains/Arch/Mips.cpp (+4)
(modified) clang/lib/Driver/ToolChains/Gnu.cpp (+3-1)
(modified) clang/test/Driver/mips-abi.c (+24)
(modified) llvm/docs/ReleaseNotes.md (+2)
(modified) llvm/lib/Target/Mips/Mips.td (+10)
(modified) llvm/lib/Target/Mips/MipsSubtarget.h (+1-1)

diff --git a/clang/lib/Basic/Targets/Mips.cpp b/clang/lib/Basic/Targets/Mips.cpp
index 866be53c8a363..08f9e3c29d1ed 100644
--- a/clang/lib/Basic/Targets/Mips.cpp
+++ b/clang/lib/Basic/Targets/Mips.cpp
@@ -47,6 +47,8 @@ bool MipsTargetInfo::processorSupportsGPR64() const {
       .Case("mips64r6", true)
       .Case("octeon", true)
       .Case("octeon+", true)
+      .Case("i6400", true)
+      .Case("i6500", true)
       .Default(false);
 }
 
@@ -54,7 +56,7 @@ static constexpr llvm::StringLiteral ValidCPUNames[] = {
     {"mips1"},  {"mips2"},    {"mips3"},    {"mips4"},    {"mips5"},
     {"mips32"}, {"mips32r2"}, {"mips32r3"}, {"mips32r5"}, {"mips32r6"},
     {"mips64"}, {"mips64r2"}, {"mips64r3"}, {"mips64r5"}, {"mips64r6"},
-    {"octeon"}, {"octeon+"}, {"p5600"}};
+    {"octeon"}, {"octeon+"},  {"p5600"},    {"i6400"},    {"i6500"}};
 
 bool MipsTargetInfo::isValidCPUName(StringRef Name) const {
   return llvm::is_contained(ValidCPUNames, Name);
diff --git a/clang/lib/Driver/ToolChains/Arch/Mips.cpp b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
index ca0745fc2b32d..9c817f238524c 100644
--- a/clang/lib/Driver/ToolChains/Arch/Mips.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
@@ -104,6 +104,8 @@ void mips::getMipsCPUAndABI(const ArgList &Args, const llvm::Triple &Triple,
                   .Case("mips64r6", "n64")
                   .Case("octeon", "n64")
                   .Case("p5600", "o32")
+                  .Case("i6400", "n64")
+                  .Case("i6500", "n64")
                   .Default("");
   }
 
@@ -514,5 +516,7 @@ bool mips::supportsIndirectJumpHazardBarrier(StringRef &CPU) {
       .Case("mips64r6", true)
       .Case("octeon", true)
       .Case("p5600", true)
+      .Case("i6400", true)
+      .Case("i6500", true)
       .Default(false);
 }
diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp b/clang/lib/Driver/ToolChains/Gnu.cpp
index f56eeda3cb5f6..68c288f516fba 100644
--- a/clang/lib/Driver/ToolChains/Gnu.cpp
+++ b/clang/lib/Driver/ToolChains/Gnu.cpp
@@ -1501,7 +1501,9 @@ bool clang::driver::findMIPSMultilibs(const Driver &D,
                       CPUName == "mips64r5" || CPUName == "octeon" ||
                       CPUName == "octeon+",
                   "-march=mips64r2", Flags);
-  addMultilibFlag(CPUName == "mips64r6", "-march=mips64r6", Flags);
+  addMultilibFlag(CPUName == "mips64r6" || CPUName == "i6400" ||
+                      CPUName == "i6500",
+                  "-march=mips64r6", Flags);
   addMultilibFlag(isMicroMips(Args), "-mmicromips", Flags);
   addMultilibFlag(tools::mips::isUCLibc(Args), "-muclibc", Flags);
   addMultilibFlag(tools::mips::isNaN2008(D, Args, TargetTriple), "-mnan=2008",
diff --git a/clang/test/Driver/mips-abi.c b/clang/test/Driver/mips-abi.c
index 06570b50928a1..9a2180c516a61 100644
--- a/clang/test/Driver/mips-abi.c
+++ b/clang/test/Driver/mips-abi.c
@@ -121,6 +121,30 @@
 // MIPS-ARCH-P5600-N64: error: ABI 'n64' is not supported on CPU 'p5600'
 //
 // RUN: %clang --target=mips-linux-gnu -### -c %s \
+// RUN:        -march=i6400 2>&1 \
+// RUN:   | FileCheck -check-prefix=MIPS-ARCH-I6400 %s
+// MIPS-ARCH-I6400: "-target-cpu" "i6400"
+// MIPS-ARCH-I6400: "-target-abi" "o32"
+//
+// RUN: %clang --target=mips-linux-gnu -### -c %s \
+// RUN:        -march=i6400 -mabi=64 2>&1 \
+// RUN:   | FileCheck -check-prefix=MIPS-ARCH-I6400-N64 %s
+// MIPS-ARCH-I6400-N64: "-target-cpu" "i6400"
+// MIPS-ARCH-I6400-N64: "-target-abi" "n64"
+//
+// RUN: %clang --target=mips-linux-gnu -### -c %s \
+// RUN:        -march=i6500 2>&1 \
+// RUN:   | FileCheck -check-prefix=MIPS-ARCH-I6500 %s
+// MIPS-ARCH-I6500: "-target-cpu" "i6500"
+// MIPS-ARCH-I6500: "-target-abi" "o32"
+//
+// RUN: %clang --target=mips-linux-gnu -### -c %s \
+// RUN:        -march=i6500 -mabi=64 2>&1 \
+// RUN:   | FileCheck -check-prefix=MIPS-ARCH-I6500-N64 %s
+// MIPS-ARCH-I6500-N64: "-target-cpu" "i6500"
+// MIPS-ARCH-I6500-N64: "-target-abi" "n64"
+//
+// RUN: %clang --target=mips-linux-gnu -### -c %s \
 // RUN:        -march=mips64 2>&1 \
 // RUN:   | FileCheck -check-prefix=MIPS-ARCH-3264 %s
 // MIPS-ARCH-3264: "-target-cpu" "mips64"
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index d7a80ae93aa34..d23019785e33d 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -101,6 +101,8 @@ Changes to the LoongArch Backend
 Changes to the MIPS Backend
 ---------------------------
 
+* `-mcpu=i6400` and `-mcpu=i6500` was added.
+
 Changes to the PowerPC Backend
 ------------------------------
 
diff --git a/llvm/lib/Target/Mips/Mips.td b/llvm/lib/Target/Mips/Mips.td
index 923e0c9cdde75..15e510ee263bc 100644
--- a/llvm/lib/Target/Mips/Mips.td
+++ b/llvm/lib/Target/Mips/Mips.td
@@ -238,6 +238,14 @@ def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl",
                                  "MipsSubtarget::CPU::P5600",
                                  "The P5600 Processor", [FeatureMips32r5]>;
 
+def ImplI6400
+    : SubtargetFeature<"i6400", "ProcImpl", "MipsSubtarget::CPU::I6400",
+                       "The I6400 Processor", [FeatureMips64r6]>;
+
+def ImplI6500
+    : SubtargetFeature<"i6500", "ProcImpl", "MipsSubtarget::CPU::I6400",
+                       "The I6500 Processor", [FeatureMips64r6]>;
+
 class Proc<string Name, list<SubtargetFeature> Features>
  : ProcessorModel<Name, MipsGenericModel, Features>;
 
@@ -261,6 +269,8 @@ def : Proc<"mips64r6", [FeatureMips64r6]>;
 def : Proc<"octeon", [FeatureMips64r2, FeatureCnMips]>;
 def : Proc<"octeon+", [FeatureMips64r2, FeatureCnMips, FeatureCnMipsP]>;
 def : ProcessorModel<"p5600", MipsP5600Model, [ImplP5600]>;
+def : ProcessorModel<"i6400", NoSchedModel, [ImplI6400]>;
+def : ProcessorModel<"i6500", NoSchedModel, [ImplI6500]>;
 
 def MipsAsmParser : AsmParser {
   let ShouldEmitMatchRegisterName = 0;
diff --git a/llvm/lib/Target/Mips/MipsSubtarget.h b/llvm/lib/Target/Mips/MipsSubtarget.h
index 85cf45d4702ae..0c75597d3decf 100644
--- a/llvm/lib/Target/Mips/MipsSubtarget.h
+++ b/llvm/lib/Target/Mips/MipsSubtarget.h
@@ -43,7 +43,7 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
     Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
   };
 
-  enum class CPU { P5600 };
+  enum class CPU { P5600, I6400 };
 
   // Used to avoid printing dsp warnings multiple times.
   static bool DspWarningPrinted;

djtodoro

Thanks for working on this.

clang/lib/Basic/Targets/Mips.cpp

clang/lib/Driver/ToolChains/Gnu.cpp

djtodoro · 2025-03-10T12:09:58Z

llvm/lib/Target/Mips/MipsSubtarget.h

@@ -43,7 +43,7 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
    Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
  };

-  enum class CPU { P5600 };
+  enum class CPU { P5600, I6400 };


do we need "i6500" here as well?

i6500 is just a multi-cluster version of i6400, right?

Please also attach/link documentation files for those CPUs.

Thanks for quick review!
yes. i6500 is multi-cluster version of i6400 and both are based on MIPS64 Release 6 ISA.
Hence I kept single subtarget I6400 and reused it in Mips.td for both i6400 and i6500.
I have added comments in the changed file MipsSubTarget.h

So, we do not use this in this patch at all, right? If that is the case, please leave this change for the Sched. Model PR.

Hi, we need this change in Mips.td as we are defining 2 new cpu (i6400 and i6500) with NoSchedModel.
In the third commit, I have defined single SubTargetFeature and reused it for both i6400 and i6500 as both are based on same CPU.
Please review.

I6400 and I6500 are based on MIPS64R6 ISA. I6500 is just multi-cluster version of I6400. Hence defined single subtarget I6400

brad0 · 2025-03-12T03:47:14Z

llvm/docs/ReleaseNotes.md

@@ -101,6 +101,8 @@ Changes to the LoongArch Backend
 Changes to the MIPS Backend
 ---------------------------

+* `-mcpu=i6400` and `-mcpu=i6500` was added.


Were instead of was.

Hi, thanks for the feedback. I have corrected it in the 3rd commit.

i6500 is multicluster version of i6400. Both use same CPU. Hence use same SubTargetFeature for both cpu definitions. Updated ReleaseNotes.md

djtodoro · 2025-03-12T09:12:45Z

llvm/lib/Target/Mips/Mips.td

@@ -238,13 +238,10 @@ def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl",
                                 "MipsSubtarget::CPU::P5600",
                                 "The P5600 Processor", [FeatureMips32r5]>;

+// I6500 is multicluster version of I6400. Both are based on same CPU.


nit: The I6500 is the multi-cluster version of the I6400. Both are based on the same CPU architecture.

updated the comments

djtodoro · 2025-03-19T07:52:25Z

Lets wait another day or two, since someone may have additional comments. Thanks @mgoudar!

mgoudar · 2025-03-19T08:40:11Z

Lets wait another day or two, since someone may have additional comments. Thanks @mgoudar!

sure. thank you.

clang/test/Driver/mips-abi.c

Default abi for mips64-gnu-linux is n64

yingopq · 2025-03-20T02:04:05Z

LGTM.

github-actions · 2025-03-21T03:08:54Z

@mgoudar Congratulations on having your first Pull Request (PR) merged into the LLVM Project!

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mgoudar · 2025-03-21T04:00:14Z

thank you.

PR llvm#130587 defined same SubTargetFeature for CPUs i6400 and i6500 which resulted into following warning when -mcpu=i6500 was used: +i6500' is not a recognized feature for this target (ignoring feature) This PR fixes above issue by defining separate SubTargetFeature for i6500.

PR #130587 defined same SubTargetFeature for CPUs i6400 and i6500 which resulted into following warning when -mcpu=i6500 was used: +i6500' is not a recognized feature for this target (ignoring feature) This PR fixes above issue by defining separate SubTargetFeature for i6500.

Relands llvm#132907 with a fix in the testcase: clang/test/CodeGen/Mips/subtarget-feature-test.c enable this test for only mips64 target PR llvm#130587 defined same SubTargetFeature for CPUs i6400 and i6500 which resulted into following warning when -mcpu=i6500 was used: +i6500' is not a recognized feature for this target (ignoring feature) This PR fixes above issue by defining separate SubTargetFeature for i6500.

Relands #132907 with a fix in the testcase: clang/test/CodeGen/Mips/subtarget-feature-test.c enable this test for only mips64 target PR #130587 defined same SubTargetFeature for CPUs i6400 and i6500 which resulted into following warning when -mcpu=i6500 was used: +i6500' is not a recognized feature for this target (ignoring feature) This PR fixes above issue by defining separate SubTargetFeature for i6500.

llvmbot added clang Clang issues not falling into any other category clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang:frontend Language frontend issues, e.g. anything involving "Sema" labels Mar 10, 2025

djtodoro added the backend:MIPS label Mar 10, 2025

djtodoro requested changes Mar 10, 2025

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djtodoro requested a review from topperc March 10, 2025 12:10

[MIPS] Add comments to MipsSubTarget.h changes

73338e1

I6400 and I6500 are based on MIPS64R6 ISA. I6500 is just multi-cluster version of I6400. Hence defined single subtarget I6400

mgoudar force-pushed the pr/add-mips-i6500-cpu branch from d365746 to 73338e1 Compare March 10, 2025 16:29

brad0 reviewed Mar 12, 2025

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[MIPS] Use single SubTargetFeature for both i6400 and i6500

97e5e91

i6500 is multicluster version of i6400. Both use same CPU. Hence use same SubTargetFeature for both cpu definitions. Updated ReleaseNotes.md

mgoudar requested review from brad0 and djtodoro March 12, 2025 07:32

djtodoro reviewed Mar 12, 2025

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[MIPS] Update comments in Mips.td

e7442a7

mgoudar requested a review from djtodoro March 12, 2025 10:09

djtodoro approved these changes Mar 19, 2025

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brad0 requested a review from yingopq March 19, 2025 07:58

yingopq reviewed Mar 19, 2025

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clang/test/Driver/mips-abi.c Show resolved Hide resolved

[MIPS] Add test to validate abi for --target mips64-gnu-linux

9c8ca52

Default abi for mips64-gnu-linux is n64

mgoudar requested a review from yingopq March 19, 2025 15:29

brad0 merged commit 0ca10ef into llvm:main Mar 21, 2025
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mgoudar mentioned this pull request Mar 25, 2025

[MIPS] Define SubTargetFeature for i6500 cpu #132907

Merged

mgoudar mentioned this pull request Mar 28, 2025

Reland [MIPS] Define SubTargetFeature for i6500 cpu (#132907) #133366

Merged

[MIPS] Add MIPS i6400 and i6500 processors #130587

[MIPS] Add MIPS i6400 and i6500 processors #130587

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