Skip to content

[AMDGPU] Update ASAN tests with update_test_checks. #68688

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom
Merged
merged 1 commit into from
Oct 12, 2023
Merged

[AMDGPU] Update ASAN tests with update_test_checks. #68688

merged 1 commit into from
Oct 12, 2023

Conversation

vpykhtin
Copy link
Contributor

I'm going to change instrumentation code for AMDGPU ASAN checks, updating existing tests to make further reviews easier.

This is my first pull request here, please, don't kill me.

@llvmbot
Copy link
Member

llvmbot commented Oct 10, 2023

@llvm/pr-subscribers-backend-amdgpu

Author: Valery (vpykhtin)

Changes

I'm going to change instrumentation code for AMDGPU ASAN checks, updating existing tests to make further reviews easier.

This is my first pull request here, please, don't kill me.

Full diff: https://github.com/llvm/llvm-project/pull/68688.diff

3 Files Affected:

  • (modified) llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_constant_address_space.ll (+25-23)
  • (modified) llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_generic_address_space.ll (+65-57)
  • (modified) llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_global_address_space.ll (+47-46)
diff --git a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_constant_address_space.ll b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_constant_address_space.ll
index bf2038994a935ee..911e8021a7361d9 100644
--- a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_constant_address_space.ll
+++ b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_constant_address_space.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
 ; RUN: opt < %s -passes=asan -S | FileCheck %s
 target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8"
 target triple = "amdgcn-amd-amdhsa"
@@ -5,30 +6,31 @@ target triple = "amdgcn-amd-amdhsa"
 @x = addrspace(4) global [2 x i32] zeroinitializer, align 4
 
 define protected amdgpu_kernel void @constant_load(i64 %i) sanitize_address {
-entry:
-; CHECK-LABEL: @constant_load
-; CHECK-NOT: load
-;
-; CHECK:   %[[LOAD_ADDR:[^ ]*]] = ptrtoint ptr addrspace(4) %a to i64
-; CHECK:   lshr i64 %[[LOAD_ADDR]], 3
-; CHECK:   add i64 %{{.*}}, 2147450880
-; CHECK:   %[[LOAD_SHADOW_PTR:[^ ]*]] = inttoptr
-; CHECK:   %[[LOAD_SHADOW:[^ ]*]] = load i8, ptr %[[LOAD_SHADOW_PTR]]
-; CHECK:   icmp ne i8
-; CHECK:   br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
-;
-; CHECK:   add i64 %{{.*}}, 3
-; CHECK:   trunc i64 %{{.*}} to i8
-; CHECK:   icmp sge i8 %{{.*}}, %[[LOAD_SHADOW]]
-; CHECK:   br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
+; CHECK-LABEL: define protected amdgpu_kernel void @constant_load(
+; CHECK-SAME: i64 [[I:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[A:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(4) @x, i64 0, i64 [[I]]
+; CHECK-NEXT:    [[TMP0:%.*]] = ptrtoint ptr addrspace(4) [[A]] to i64
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr i64 [[TMP0]], 3
+; CHECK-NEXT:    [[TMP2:%.*]] = add i64 [[TMP1]], 2147450880
+; CHECK-NEXT:    [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr
+; CHECK-NEXT:    [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 1
+; CHECK-NEXT:    [[TMP5:%.*]] = icmp ne i8 [[TMP4]], 0
+; CHECK-NEXT:    br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP12:%.*]], !prof [[PROF1:![0-9]+]]
+; CHECK:       6:
+; CHECK-NEXT:    [[TMP7:%.*]] = and i64 [[TMP0]], 7
+; CHECK-NEXT:    [[TMP8:%.*]] = add i64 [[TMP7]], 3
+; CHECK-NEXT:    [[TMP9:%.*]] = trunc i64 [[TMP8]] to i8
+; CHECK-NEXT:    [[TMP10:%.*]] = icmp sge i8 [[TMP9]], [[TMP4]]
+; CHECK-NEXT:    br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP12]]
+; CHECK:       11:
+; CHECK-NEXT:    call void @__asan_report_load4(i64 [[TMP0]]) #[[ATTR3:[0-9]+]]
+; CHECK-NEXT:    unreachable
+; CHECK:       12:
+; CHECK-NEXT:    [[Q:%.*]] = load i32, ptr addrspace(4) [[A]], align 4
+; CHECK-NEXT:    ret void
 ;
-; The crash block reports the error.
-; CHECK:   call void @__asan_report_load4(i64 %[[LOAD_ADDR]])
-; CHECK:   unreachable
-;
-; The actual load.
-; CHECK:   load i32, ptr addrspace(4) %a
-; CHECK:   ret void
+entry:
 
   %a = getelementptr inbounds [2 x i32], ptr  addrspace(4) @x, i64 0, i64 %i
   %q = load i32, ptr addrspace(4) %a, align 4
diff --git a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_generic_address_space.ll b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_generic_address_space.ll
index 465d7c9c4eb66ae..34b7f04592e25cc 100644
--- a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_generic_address_space.ll
+++ b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_generic_address_space.ll
@@ -1,38 +1,42 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
 ; RUN: opt < %s -passes=asan -S | FileCheck %s
 target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8"
 target triple = "amdgcn-amd-amdhsa"
 
 define protected amdgpu_kernel void @generic_store(ptr addrspace(1) %p, i32 %i) sanitize_address {
-entry:
-; CHECK-LABEL: @generic_store
-; CHECK-NOT: store
-; CHECK:   %[[GENERIC_ADDR:[^ ]*]] = addrspacecast ptr addrspace(1) %p to ptr
-; CHECK:   call i1 @llvm.amdgcn.is.shared(ptr %[[GENERIC_ADDR]])
-; CHECK:   call i1 @llvm.amdgcn.is.private(ptr %[[GENERIC_ADDR]])
-; CHECK:   or
-; CHECK:   xor i1 %{{.*}}, true
-; CHECK:   br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
-;
-; CHECK:   %[[STORE_ADDR:[^ ]*]] = ptrtoint ptr %q to i64
-; CHECK:   lshr i64 %[[STORE_ADDR]], 3
-; CHECK:   add i64 %{{.*}}, 2147450880
-; CHECK:   %[[STORE_SHADOW_PTR:[^ ]*]] = inttoptr
-; CHECK:   %[[STORE_SHADOW:[^ ]*]] = load i8, ptr %[[STORE_SHADOW_PTR]]
-; CHECK:   icmp ne i8
-; CHECK:   br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
-;
-; CHECK:   add i64 %{{.*}}, 3
-; CHECK:   trunc i64 %{{.*}} to i8
-; CHECK:   icmp sge i8 %{{.*}}, %[[STORE_SHADOW]]
-; CHECK:   br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
+; CHECK-LABEL: define protected amdgpu_kernel void @generic_store(
+; CHECK-SAME: ptr addrspace(1) [[P:%.*]], i32 [[I:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[Q:%.*]] = addrspacecast ptr addrspace(1) [[P]] to ptr
+; CHECK-NEXT:    [[TMP0:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[Q]])
+; CHECK-NEXT:    [[TMP1:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[Q]])
+; CHECK-NEXT:    [[TMP2:%.*]] = or i1 [[TMP0]], [[TMP1]]
+; CHECK-NEXT:    [[TMP3:%.*]] = xor i1 [[TMP2]], true
+; CHECK-NEXT:    br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP18:%.*]]
+; CHECK:       4:
+; CHECK-NEXT:    [[TMP5:%.*]] = ptrtoint ptr [[Q]] to i64
+; CHECK-NEXT:    [[TMP6:%.*]] = lshr i64 [[TMP5]], 3
+; CHECK-NEXT:    [[TMP7:%.*]] = add i64 [[TMP6]], 2147450880
+; CHECK-NEXT:    [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr
+; CHECK-NEXT:    [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 1
+; CHECK-NEXT:    [[TMP10:%.*]] = icmp ne i8 [[TMP9]], 0
+; CHECK-NEXT:    br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP17:%.*]], !prof [[PROF0:![0-9]+]]
+; CHECK:       11:
+; CHECK-NEXT:    [[TMP12:%.*]] = and i64 [[TMP5]], 7
+; CHECK-NEXT:    [[TMP13:%.*]] = add i64 [[TMP12]], 3
+; CHECK-NEXT:    [[TMP14:%.*]] = trunc i64 [[TMP13]] to i8
+; CHECK-NEXT:    [[TMP15:%.*]] = icmp sge i8 [[TMP14]], [[TMP9]]
+; CHECK-NEXT:    br i1 [[TMP15]], label [[TMP16:%.*]], label [[TMP17]]
+; CHECK:       16:
+; CHECK-NEXT:    call void @__asan_report_store4(i64 [[TMP5]]) #[[ATTR3:[0-9]+]]
+; CHECK-NEXT:    unreachable
+; CHECK:       17:
+; CHECK-NEXT:    br label [[TMP18]]
+; CHECK:       18:
+; CHECK-NEXT:    store i32 0, ptr [[Q]], align 4
+; CHECK-NEXT:    ret void
 ;
-; The crash block reports the error.
-; CHECK:   call void @__asan_report_store4(i64 %[[STORE_ADDR]])
-; CHECK:   unreachable
-;
-; The actual store.
-; CHECK:   store i32 0, ptr %q
-; CHECK:   ret void
+entry:
 
   %q = addrspacecast ptr addrspace(1) %p to ptr
   store i32 0, ptr %q, align 4
@@ -40,35 +44,39 @@ entry:
 }
 
 define protected amdgpu_kernel void @generic_load(ptr addrspace(1) %p, i32 %i) sanitize_address {
-entry:
-; CHECK-LABEL: @generic_load
-; CHECK-NOT: load
-; CHECK:   call i1 @llvm.amdgcn.is.shared(ptr %[[GENERIC_ADDR]])
-; CHECK:   call i1 @llvm.amdgcn.is.private(ptr %[[GENERIC_ADDR]])
-; CHECK:   or
-; CHECK:   xor i1 %{{.*}}, true
-; CHECK:   br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
-;
-; CHECK:   %[[STORE_ADDR:[^ ]*]] = ptrtoint ptr %q to i64
-; CHECK:   lshr i64 %[[STORE_ADDR]], 3
-; CHECK:   add i64 %{{.*}}, 2147450880
-; CHECK:   %[[STORE_SHADOW_PTR:[^ ]*]] = inttoptr
-; CHECK:   %[[STORE_SHADOW:[^ ]*]] = load i8, ptr %[[STORE_SHADOW_PTR]]
-; CHECK:   icmp ne i8
-; CHECK:   br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
-;
-; CHECK:   add i64 %{{.*}}, 3
-; CHECK:   trunc i64 %{{.*}} to i8
-; CHECK:   icmp sge i8 %{{.*}}, %[[STORE_SHADOW]]
-; CHECK:   br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
+; CHECK-LABEL: define protected amdgpu_kernel void @generic_load(
+; CHECK-SAME: ptr addrspace(1) [[P:%.*]], i32 [[I:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[Q:%.*]] = addrspacecast ptr addrspace(1) [[P]] to ptr
+; CHECK-NEXT:    [[TMP0:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[Q]])
+; CHECK-NEXT:    [[TMP1:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[Q]])
+; CHECK-NEXT:    [[TMP2:%.*]] = or i1 [[TMP0]], [[TMP1]]
+; CHECK-NEXT:    [[TMP3:%.*]] = xor i1 [[TMP2]], true
+; CHECK-NEXT:    br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP18:%.*]]
+; CHECK:       4:
+; CHECK-NEXT:    [[TMP5:%.*]] = ptrtoint ptr [[Q]] to i64
+; CHECK-NEXT:    [[TMP6:%.*]] = lshr i64 [[TMP5]], 3
+; CHECK-NEXT:    [[TMP7:%.*]] = add i64 [[TMP6]], 2147450880
+; CHECK-NEXT:    [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr
+; CHECK-NEXT:    [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 1
+; CHECK-NEXT:    [[TMP10:%.*]] = icmp ne i8 [[TMP9]], 0
+; CHECK-NEXT:    br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP17:%.*]], !prof [[PROF0]]
+; CHECK:       11:
+; CHECK-NEXT:    [[TMP12:%.*]] = and i64 [[TMP5]], 7
+; CHECK-NEXT:    [[TMP13:%.*]] = add i64 [[TMP12]], 3
+; CHECK-NEXT:    [[TMP14:%.*]] = trunc i64 [[TMP13]] to i8
+; CHECK-NEXT:    [[TMP15:%.*]] = icmp sge i8 [[TMP14]], [[TMP9]]
+; CHECK-NEXT:    br i1 [[TMP15]], label [[TMP16:%.*]], label [[TMP17]]
+; CHECK:       16:
+; CHECK-NEXT:    call void @__asan_report_load4(i64 [[TMP5]]) #[[ATTR3]]
+; CHECK-NEXT:    unreachable
+; CHECK:       17:
+; CHECK-NEXT:    br label [[TMP18]]
+; CHECK:       18:
+; CHECK-NEXT:    [[R:%.*]] = load i32, ptr [[Q]], align 4
+; CHECK-NEXT:    ret void
 ;
-; The crash block reports the error.
-; CHECK:   call void @__asan_report_load4(i64 %[[STORE_ADDR]])
-; CHECK:   unreachable
-;
-; The actual store.
-; CHECK:   load i32, ptr %q
-; CHECK:   ret void
+entry:
 
   %q = addrspacecast ptr addrspace(1) %p to ptr
   %r = load i32, ptr %q, align 4
diff --git a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_global_address_space.ll b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_global_address_space.ll
index a051b4197098dcc..d8708e7448355bd 100644
--- a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_global_address_space.ll
+++ b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_global_address_space.ll
@@ -1,62 +1,63 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
 ; RUN: opt < %s -passes=asan -S | FileCheck %s
 target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8"
 target triple = "amdgcn-amd-amdhsa"
 
 define protected amdgpu_kernel void @global_store(ptr addrspace(1) %p, i32 %i) sanitize_address {
-entry:
-; CHECK-LABEL: @global_store
-; CHECK-NOT: store
-;
-; CHECK:   %[[STORE_ADDR:[^ ]*]] = ptrtoint ptr addrspace(1) %p to i64
-; CHECK:   lshr i64 %[[STORE_ADDR]], 3
-; CHECK:   add i64 %{{.*}}, 2147450880
-; CHECK:   %[[STORE_SHADOW_PTR:[^ ]*]] = inttoptr
-; CHECK:   %[[STORE_SHADOW:[^ ]*]] = load i8, ptr %[[STORE_SHADOW_PTR]]
-; CHECK:   icmp ne i8
-; CHECK:   br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
-;
-; CHECK:   add i64 %{{.*}}, 3
-; CHECK:   trunc i64 %{{.*}} to i8
-; CHECK:   icmp sge i8 %{{.*}}, %[[STORE_SHADOW]]
-; CHECK:   br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
+; CHECK-LABEL: define protected amdgpu_kernel void @global_store(
+; CHECK-SAME: ptr addrspace(1) [[P:%.*]], i32 [[I:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = ptrtoint ptr addrspace(1) [[P]] to i64
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr i64 [[TMP0]], 3
+; CHECK-NEXT:    [[TMP2:%.*]] = add i64 [[TMP1]], 2147450880
+; CHECK-NEXT:    [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr
+; CHECK-NEXT:    [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 1
+; CHECK-NEXT:    [[TMP5:%.*]] = icmp ne i8 [[TMP4]], 0
+; CHECK-NEXT:    br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP12:%.*]], !prof [[PROF0:![0-9]+]]
+; CHECK:       6:
+; CHECK-NEXT:    [[TMP7:%.*]] = and i64 [[TMP0]], 7
+; CHECK-NEXT:    [[TMP8:%.*]] = add i64 [[TMP7]], 3
+; CHECK-NEXT:    [[TMP9:%.*]] = trunc i64 [[TMP8]] to i8
+; CHECK-NEXT:    [[TMP10:%.*]] = icmp sge i8 [[TMP9]], [[TMP4]]
+; CHECK-NEXT:    br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP12]]
+; CHECK:       11:
+; CHECK-NEXT:    call void @__asan_report_store4(i64 [[TMP0]]) #[[ATTR3:[0-9]+]]
+; CHECK-NEXT:    unreachable
+; CHECK:       12:
+; CHECK-NEXT:    store i32 0, ptr addrspace(1) [[P]], align 4
+; CHECK-NEXT:    ret void
 ;
-; The crash block reports the error.
-; CHECK:   call void @__asan_report_store4(i64 %[[STORE_ADDR]])
-; CHECK:   unreachable
-;
-; The actual store.
-; CHECK:   store i32 0, ptr addrspace(1) %p
-; CHECK:   ret void
+entry:
 
   store i32 0, ptr addrspace(1) %p, align 4
   ret void
 }
 
 define protected amdgpu_kernel void @global_load(ptr addrspace(1) %p, i32 %i) sanitize_address {
-entry:
-; CHECK-LABEL: @global_load
-; CHECK-NOT: load
-;
-; CHECK:   %[[LOAD_ADDR:[^ ]*]] = ptrtoint ptr addrspace(1) %p to i64
-; CHECK:   lshr i64 %[[LOAD_ADDR]], 3
-; CHECK:   add i64 %{{.*}}, 2147450880
-; CHECK:   %[[LOAD_SHADOW_PTR:[^ ]*]] = inttoptr
-; CHECK:   %[[LOAD_SHADOW:[^ ]*]] = load i8, ptr %[[LOAD_SHADOW_PTR]]
-; CHECK:   icmp ne i8
-; CHECK:   br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
-;
-; CHECK:   add i64 %{{.*}}, 3
-; CHECK:   trunc i64 %{{.*}} to i8
-; CHECK:   icmp sge i8 %{{.*}}, %[[LOAD_SHADOW]]
-; CHECK:   br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
+; CHECK-LABEL: define protected amdgpu_kernel void @global_load(
+; CHECK-SAME: ptr addrspace(1) [[P:%.*]], i32 [[I:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = ptrtoint ptr addrspace(1) [[P]] to i64
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr i64 [[TMP0]], 3
+; CHECK-NEXT:    [[TMP2:%.*]] = add i64 [[TMP1]], 2147450880
+; CHECK-NEXT:    [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr
+; CHECK-NEXT:    [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 1
+; CHECK-NEXT:    [[TMP5:%.*]] = icmp ne i8 [[TMP4]], 0
+; CHECK-NEXT:    br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP12:%.*]], !prof [[PROF0]]
+; CHECK:       6:
+; CHECK-NEXT:    [[TMP7:%.*]] = and i64 [[TMP0]], 7
+; CHECK-NEXT:    [[TMP8:%.*]] = add i64 [[TMP7]], 3
+; CHECK-NEXT:    [[TMP9:%.*]] = trunc i64 [[TMP8]] to i8
+; CHECK-NEXT:    [[TMP10:%.*]] = icmp sge i8 [[TMP9]], [[TMP4]]
+; CHECK-NEXT:    br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP12]]
+; CHECK:       11:
+; CHECK-NEXT:    call void @__asan_report_load4(i64 [[TMP0]]) #[[ATTR3]]
+; CHECK-NEXT:    unreachable
+; CHECK:       12:
+; CHECK-NEXT:    [[Q:%.*]] = load i32, ptr addrspace(1) [[P]], align 4
+; CHECK-NEXT:    ret void
 ;
-; The crash block reports the error.
-; CHECK:   call void @__asan_report_load4(i64 %[[LOAD_ADDR]])
-; CHECK:   unreachable
-;
-; The actual load.
-; CHECK:   load i32, ptr addrspace(1) %p
-; CHECK:   ret void
+entry:
 
   %q = load i32, ptr addrspace(1) %p, align 4
   ret void

jayfoad
jayfoad approved these changes Oct 10, 2023
View reviewed changes
Copy link
Contributor

@jayfoad jayfoad left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

LGTM

@vpykhtin vpykhtin merged commit b9bc1ce into llvm:main Oct 12, 2023
@vpykhtin vpykhtin deleted the update_asan_tests branch October 12, 2023 11:16
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Reviewers

@jayfoad jayfoad jayfoad approved these changes

@arsenm arsenm Awaiting requested review from arsenm

@rksharma-yymd rksharma-yymd Awaiting requested review from rksharma-yymd

Assignees
No one assigned
Labels
backend:AMDGPU
Projects
None yet
Milestone
No milestone
Development

Successfully merging this pull request may close these issues.
3 participants
@vpykhtin @llvmbot @jayfoad